X5001V8IZ-2.7 INTERSIL [Intersil Corporation], X5001V8IZ-2.7 Datasheet - Page 13

• Manufacturer Part Number: X5001V8IZ-2.7
• Description: CPU Supervisor
• Manufacturer: INTERSIL [Intersil Corporation]

Data Output Timing
Notes: (3) This parameter is periodically sampled and not 100% tested.
Figure 10. Data Output Timing
Figure 11. Data Input Timing
Symbol
t
t
f
RO
FO
t
t
SCK
DIS
(4) t
SCK
SCK
HO
t
V
CS
SO
SO
CS
(3)
(3)
SI
SI
write cycle.
WC
is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
LSB IN
ADDR
Clock frequency
Output disable time
Output valid from clock low
Output hold time
Output rise time
Output fall time
t
SU
High Impedance
MSB In
13
MSB Out
t
LEAD
Parameter
t
V
t
H
t
CYC
MSB–1 Out
t
X5001
HO
Min.
0
0
1.8V-3.6V
t
RI
t
WH
Max.
400
400
300
300
1
t
WL
t
FI
Min.
LSB In
0
0
LSB Out
2.7V-5.5V
t
CS
Max.
200
200
150
150
2
t
LAG
t
t
DIS
LAG
Unit
MHz
ns
ns
ns
ns
ns
May 30, 2006
FN8125.1