X5001V8IZ-2.7 INTERSIL [Intersil Corporation], X5001V8IZ-2.7 Datasheet - Page 4

• Manufacturer Part Number: X5001V8IZ-2.7
• Description: CPU Supervisor
• Manufacturer: INTERSIL [Intersil Corporation]

PIN CONFIGURATION
PIN DESCRIPTION
(SOIC/PDIP)
Pin
1
2
5
6
3
4
8
7
3-5,10-12
TSSOP
CS/WDI
RESET
Pin
14
13
1
2
8
9
6
7
V
SO
CC
4
CS/WDI
RESET
8 Ld TSSOP
1
2
3
4
Name
SCK
V
V
V
SO
NC
SI
CC
PE
SS
X5001
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the device
will be in the standby power mode. CS LOW enables the device, placing it in the
active power mode. Prior to the start of any operation after power-up, a HIGH to
LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watch-
dog timer. The absence of a HIGH to LOW transition within the watchdog time
out period results in RESET/RESET going active.
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data
out on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the
input data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock. The Serial Clock controls the serial bus timing for data input and
output. The rising edge of SCK latches in the opcode, address, or watchdog bits
present on the SI pin. The falling edge of SCK changes the data output on the
SO pin.
V
valid programmed level. To readjust the V
pulled to a high voltage (15-18V).
Ground
Supply Voltage
Reset Output. RESET is an active LOW, open drain output which goes active
whenever V
til V
if the watchdog timer is enabled and CS/WDI remains either HIGH or LOW long-
er than the selectable watchdog time out period. A falling edge of CS/WDI will
reset the watchdog timer. RESET goes active on power-up at 1V and remains
active for 200ms after the power supply stabilizes.
No internal connections
TRIP
8
7
6
5
CC
Program Enable. When V
rises above the minimum V
SCK
SI
V
V
SS
PE
CC
X5001
falls below the minimum V
CS/WDI
V
V
SO
PE
SS
PE
CC
Function
is LOW, the V
8 Ld SOIC/PDIP
sense level for 200ms. RESET goes active
1
2
3
4
CC
TRIP
X5001
sense level. It will remain active un-
level, requires that the V
8
7
6
5
TRIP
point is fixed at the last
RESET
V
SCK
SI
CC
PE
May 30, 2006
pin be
FN8125.1