LF3320QC15 LODEV [LOGIC Devices Incorporated], LF3320QC15 Datasheet - Page 16

• Manufacturer Part Number: LF3320QC15
• Description: Horizontal Digital Image Filter
• Manufacturer: LODEV [LOGIC Devices Incorporated]

DEVICES INCORPORATED
of loading data into Filter B limit
register 7. Data value 3B60H is loaded
as the lower limit and 72A4H is loaded
as the upper limit.
It takes 9S clock cycles to load S
coefficient sets into the device. There-
fore, it takes 2304 clock cycles to load
all 256 coefficient sets. Assuming an
83 MHz clock rate, all 256 coefficient
F
F
F
PAUSEA/PAUSEB
CFA/CFB
IGURE
IGURE
IGURE
CFA/CFB
LDA/LDB
CFA/CFB
LDA/LDB
CLK
11-0
LDA/LDB
17. C
18. C
19. C
CLK
11-0
W1: Configuration Register loaded with new data on this rising clock edge.
W2: Select Register loaded with new data on this rising clock edge.
W3: Round Register loaded with new data on this rising clock edge.
W4: Limit Register loaded with new data on this rising clock edge.
CLK
11-0
W1: Coefficient Set 1 written to coefficient banks during this clock cycle.
W2: Coefficient Set 2 written to coefficient banks during this clock cycle.
W3: Coefficient Set 3 written to coefficient banks during this clock cycle.
W1: Coefficient Set 1 written to coefficient banks during this clock cycle.
OEFFICIENT
ONFIGURATION
OEFFICIENT
ADDR
CONFIG REG
ADDR
1
ADDR
DATA
1
1
COEFFICIENT SET 1
B
B
1
COEF
ANK
ANK
W1
ADDR
/C
SELECT REG
0
ONTROL
2
L
L
COEF
OADING
OADING
DATA
sets can be updated in less than 27.7 µs,
which is well within vertical blanking
time. It takes 5S clock cycles to load S
round or limit registers. Therefore, it
takes 320 clock cycles to update all
round and limit registers (both Filters A
and B). Assuming an 83 MHz clock
rate, all Filter A and B round/limit
registers can be updated in 3.84 µs.
0
1
R
COEF
W2
ADDR
EGISTER
S
S
EQUENCE
EQUENCE WITH
3
7
DATA
ADDR
ROUND REGISTER
W1
1
L
2
COEFFICIENT SET 2
OADING
DATA
COEF
COEF
COEFFICIENT SET 1
2-16
2
1
0
DATA
PAUSE I
S
3
EQUENCE
W3
DATA
COEF
4
MPLEMENTATION
ADDR
Horizontal Digital Image Filter
7
ADDR
4
W2
DATA
The coefficient banks and
Configuration/Control registers are not
loaded with data until all data values
for the specified address are loaded into
the LF Interface
coefficient banks are not written to until
all eight coefficients have been loaded
into the LF Interface
not written to until all four data values
are loaded.
3
COEFFICIENT SET 3
Video Imaging Products
LIMIT REGISTER
COEF
1
DATA
0
2
DATA
COEF
TM
3
COEF
. In other words, the
DATA
TM
7
. A round register is
7
4
W4
08/16/2000–LDS.3320-N
W3
LF3320
W1