XR68C192 EXAR [Exar Corporation], XR68C192 Datasheet - Page 14

• Manufacturer Part Number: XR68C192
• Description: DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
• Manufacturer: EXAR [Exar Corporation]

XR68C92/192
(address tag). The received character is discarded if the
received address/data bit is a zero (data tag). If the
receiver is enabled, all received characters are trans-
ferred to the CPU by way of the receive holding register
stack during read operations. In either case, the data
bits are loaded into the data portion of the FIFO stack
while the address/data bit is loaded into the status
portion of the FIFO stack normally used for parity error
(Status Register bit-5). Framing error, overrun error, and
break-detection operate normally regardless of whether
the receiver is enabled or disabled. The address/data bit
takes the place of the parity bit and parity is neither
calculated nor checked for characters in this mode.
COUNTER/TIMER
The 16-bit counter/timer (C/T) can operate in a
counter mode or a timer mode. In either mode, users
can program the C/T input (clock source) to come from
several sources and program the C/T output to appear
at output port pin OP3. The value (pre-load value) stored
in the concatenation of the C/T upper register (CTUR)
and the C/T lower register (CTLR) can be from 0x0001
through 0xFFFF and can be changed at any time. In
counter mode, the CPU can start and stop the C/T. This
mode allows the C/T to function as a system stopwatch,
a real-time single interrupt generator, or a device watch-
dog. In timer mode, the C/T runs continuously, the CPU
cannot start or stop it. Instead, the CPU only resets the
C/T interrupt. This mode allows the C/T to be used as a
programmable clock source for channels A and B, or
periodic interrupt generator. At power-up and after reset,
the C/T operates in timer mode.
COUNTER MODE
In counter mode, the C/T counts down from the pre-load
value using the programmed counter clock source. The
counter clock source can be the channel A transmitter
clock, the channel B transmitter clock, the external
clock on the XTAL1 pin divided by sixteen, or an external
clock on the input port pin IP2. The CPU can start and
stop the counter, and can read the count value
(CUR:CLR) if the counter is stopped. When a read at the
start counter command address is performed, the
counter is initialized to the pre-load value and begins a
countdown sequence. When the counter counts from
0x0001 to 0x0000 (terminal count), the C/T-ready bit in
the interrupt status register (ISR Bit-3) is set.
3
Users can program the counter to generate an interrupt
request for this condition on the -INT output or output pin
Rev. P1.10
14
OP3. After 0x0000 the counter counts to 0xFFFF, and
continues counting down from there. If the CPU
changes the pre-load value, the counter will not recog-
nize the new value until it receives the next start counter
command (and is reinitialized). When a read at the stop
counter command address is performed, the counter
stops the countdown sequence and clears ISR Bit-3.
The count value should only be read while the counter
is stopped because only one of the count registers
(either CUR or CLR) can be read at a time. If the counter
is running, a decrement of CLR that requires a borrow
from the CUR could take place between the two reads.
TIMER MODE
In timer mode, the C/T generates a square-wave
output derived from the programmed timer input
(clock source). The timer clock source can be the
external clock on the XTAL1 input pin divided by one
or sixteen, or it can be an external input on input port
pin IP2 divided by one or sixteen. The square wave
generated by the timer has a period of 2X (pre-load
value) X (period of clock source), is available as a
clock source for both communications channels and
can be programmed to appear on output pin OP3. The
timer runs continuously, the CPU cannot stop it.
Because the timer cannot be stopped, the count value
(CUR:CLR) should not be read. When a read at the
start counter command address is performed, the
timer terminates the current countdown sequence,
sets its output to 1 (appears un-inverted at OP3), is
initialized to the pre-load value, and begins a new
countdown sequence. When the counter counts from
0x0001 (terminal count), it inverts its output, is re-
initialized to the pre-load value and repeats the count-
down sequence.
After reaching terminal count a second time, the timer
sets the C/T-ready bit in the interrupt status register
(ISR Bit-3), inverts its output, is re-initialized again,
and begins a new countdown sequence. Users can
program the timer to generate an interrupt request for
this condition (every second countdown cycle) on the -
INT output. If the CPU changes the pre-load value, the
timer will not recognize the new value until either (a) it
reaches the next terminal count and is reinitialized
automatically, or (b) it is forced to re-initialize by a start
command. When a read at the stop counter command
address is performed, the timer clears ISR Bit-3 but
does not stop. Because in timer mode the C/T runs
continuously, it should be completely configured (pre-