XR16M752 EXAR [Exar Corporation], XR16M752 Datasheet - Page 10

• Manufacturer Part Number: XR16M752
• Description: HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

XR16M752/XR68M752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is
disabled (FCR bit-3 = 0), the M752 is placed in single-character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the programmed trigger level. In this mode, the M752
sets the TXRDY# pin when the transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO
becomes empty. The following table shows their behavior. Also see
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Table 4 and 5
through
2.5
2.6
RXRDY# A/B LOW = 1 byte.
TXRDY# A/B LOW = THR empty.
INTA/B Pin
INTA/B Pin
INTA/B Pin
P
INS
DMA Mode
INTA and INTB Outputs
24.
HIGH = no data.
HIGH = byte in THR.
summarize the operating behavior for the transmitter and receiver. Also see
Auto RS485
(FIFO D
LOW = no data
HIGH = 1 byte
FCR
Mode
YES
NO
T
ABLE
BIT
(FIFO D
ISABLED
T
FCR B
-0=0
ABLE
T
3: TXRDY#
ABLE
LOW = a byte in THR
HIGH = THR empty
LOW = a byte in THR
HIGH = transmitter empty
)
IT
ISABLED
4: INTA
-0 = 0
5: INTA
LOW = at least 1 byte in FIFO.
HIGH = FIFO empty.
LOW = FIFO empty.
HIGH = at least 1 byte in FIFO.
(FIFO D
FCR B
)
(DMA Mode Disabled)
AND
AND
AND
IT
ISABLED
FCR Bit-3 = 0
INTB P
RXRDY# O
-0 = 0
LOW = FIFO below trigger level
HIGH = FIFO above trigger level
INTB P
)
INS
10
IN
O
UTPUTS IN
O
PERATION FOR
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or FIFO empty
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or transmitter empty
PERATION
FCR B
IT
HIGH to LOW transition when FIFO reaches the
trigger level, or time-out occurs.
LOW to HIGH transition when FIFO empties or
LSR[7] = 1.
LOW = FIFO is below the trigger level.
HIGH = FIFO is full.
-0=1 (FIFO E
FIFO
Figures 19
F
FCR B
OR
(FIFO E
FCR B
T
AND
RANSMITTER
R
ECEIVER
IT
DMA M
-0 = 1 (FIFO E
(DMA Mode Enabled)
IT
NABLED
NABLED
-0 = 1
through 24.
FCR Bit-3 = 1
ODE
)
)
NABLED
)
Figures 19
REV. 1.0.2