M24L216128DA-55BEG ESMT [Elite Semiconductor Memory Technology Inc.], M24L216128DA-55BEG Datasheet - Page 7

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M24L216128DA-55BEG

Manufacturer Part Number
M24L216128DA-55BEG
Description
2-Mbit (128K x 16) Pseudo Static RAM
Manufacturer
ESMT [Elite Semiconductor Memory Technology Inc.]
Datasheet
ESMT
M24L216128DA
Switching Waveforms (continued)
Write Cycle 1 ( WE Controlled)[13, 14, 17, 18, 19]
1
Write Cycle 2 (
CE
or CE2 Controlled)[13, 14, 17, 18, 19]
Notes:
17.Data I/O is high impedance if OE ≥ V
.
IH
18.If Chip Enable goes INACTIVE with WE = HIGH, the output remains in a high-impedance state.
19.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.2
7/14

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