M24L216128DA-55BEG ESMT [Elite Semiconductor Memory Technology Inc.], M24L216128DA-55BEG Datasheet - Page 9

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M24L216128DA-55BEG

Manufacturer Part Number
M24L216128DA-55BEG
Description
2-Mbit (128K x 16) Pseudo Static RAM
Manufacturer
ESMT [Elite Semiconductor Memory Technology Inc.]
Datasheet
ESMT
Avoid Timing
shorter than tRC during over 15μs at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during
15μs shown as in Avoidable timing 1 or toggle
Abnormal Timing
Avoidable Timing 1
Avoidable Timing 2
Elite Semiconductor Memory Technology Inc.
ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal
Address
Address
Address
CE1
WE
CE1
WE
CE1
WE
< t
CE
< t
RC
1
RC
to high (≧tRC) one time at least shown as in Avoidable Timing 2.
t
RC
15μs
15μs
15μs
t
RC
Revision : 1.2
Publication Date : Jul. 2008
M24L216128DA
9/14

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