A3PE1500-1FG896 ACTEL [Actel Corporation], A3PE1500-1FG896 Datasheet - Page 61

• Manufacturer Part Number: A3PE1500-1FG896
• Description: ProASIC3E Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Figure 2-23 • LVPECL Circuit Diagram and Board-Level Implementation
Table 2-77 • Minimum and Maximum DC Input and Output Levels
Table 2-78 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-79 • LVPECL
DC Parameter
V
V
V
V
V
V
V
V
Input LOW (V)
1.64
*
Speed Grade
–F
Std.
–1
–2
Note:
OUTBUF_LVPECL
CCI
OL
OH
IL
ODIFF
OCM
ICM
IDIFF
Measuring point = V
, V
IH
For specific junction temperature and voltage supply levels, refer to
values.
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It
requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It
also requires external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
Figure
receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.
The values for the three driver resistors are different from those used in the LVDS implementation
because the output standard specifications are different.
Timing Characteristics
Commercial-Case Conditions: T
Supply Voltage
Output LOW Voltage
Output HIGH Voltage
Input LOW, Input HIGH Voltages
Differential Output Voltage
Output Common-Mode Voltage
Input Common-Mode Voltage
Input Differential Voltage
2-23. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one
FPGA
trip
. See
Table 2-15 on page 2-18
Description
N
P
Input HIGH (V)
Bourns Part Number: CAT16-PC4F12
100 Ω
100 Ω
1.94
t
0.79
0.56
0.49
DOUT
0.66
J
= 70°C, Worst-Case V
187 W
v1.2
for a complete table of trip points.
Z
Z
2.19
1.83
1.55
1.36
t
0
0.625
1.762
0
Min.
0.96
1.01
Measuring Point* (V)
DP
300
1.8
= 50 Ω
= 50 Ω
0
3.0
Cross point
Max.
1.27
2.11
0.97
1.98
2.57
CC
3.3
100 Ω
= 1.425 V, Worst-Case V
0.05
0.04
0.04
0.03
t
ProASIC3E DC and Switching Characteristics
DIN
0.625
1.762
Min.
1.06
1.92
1.01
300
0
Table 2-6 on page 2-5
N
P
3.3
Max.
1.43
2.28
0.97
1.98
2.57
3.6
FPGA
1.96
1.63
1.39
1.22
+
t
–
PY
0.625
1.762
Min.
1.30
2.13
1.01
300
V
0
REF
CCI
INBUF_LVPECL
3.6
(typ.) (V)
= 3.0 V
–
Max.
1.57
2.41
0.97
1.98
2.57
3.9
for derating
Units
ns
ns
ns
ns
Units
mV
V
V
V
V
V
V
V
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