AGLE3000V2-FFG896 ACTEL [Actel Corporation], AGLE3000V2-FFG896 Datasheet - Page 106
![no-image](/images/no-image-200.jpg)
AGLE3000V2-FFG896
Manufacturer Part Number
AGLE3000V2-FFG896
Description
IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
Manufacturer
ACTEL [Actel Corporation]
Datasheet
1.AGLE3000V2-FFG896.pdf
(156 pages)
- Current page: 106 of 156
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IGLOOe DC and Switching Characteristics
Clock Conditioning Circuits
Table 2-135 • IGLOOe CCC/PLL Specification
2 -9 2
Parameter
Clock Conditioning Circuitry Input Frequency f
Clock Conditioning Circuitry Output Frequency f
Serial Clock (SCLK) for Dynamic PLL
Delay Increments in Programmable Delay Blocks
Number of Programmable Values in Each Programmable Delay
Block
Input Cycle-to-Cycle Jitter (peak magnitude)
CCC Output Peak-to-Peak Period Jitter F
Acquisition Time
Tracking Jitter
Output Duty Cycle
Delay Range in Block: Programmable Delay 1
Delay Range in Block: Programmable Delay 2
Delay Range in Block: Fixed Delay
Notes:
1. This delay is a function of voltage and temperature. See
2. T
3. Maximum value obtained for a Std. speed grade device in Worst Case Commercial Conditions.For specific
4. For definitions of Type 1 and Type 2, refer to the PLL Block Diagram in the
5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL
for deratings.
junction temperature and voltage supply levels, refer to
IGLOO and ProASIC3 Devices
input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by
the period jitter parameter.
J
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 250 MHz
= 25°C, V
CCC Electrical Specifications
Timing Characteristics
For IGLOOe V2 or V5 Devices, 1.5 V DC Core Supply Voltage
CC
= 1.5 V
chapter of the handbook.
1, 2
3
CCC_OUT
1, 2, 4
1, 2, 4
IN_CCC
1, 2
OUT_CCC
A d v a n c e v 0. 3
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
Table 2-6 on page 2-6
Table 2-6 on page 2-6
Network
1 Global
0.50%
1.00%
2.50%
0.025
Used
Min.
0.75
1.25
48.5
1.5
Max Peak-to-Peak Period Jitter
External
FB Used
0.75%
1.50%
3.75%
Clock Conditioning Circuits in
Typ.
360
3.5
for derating values.
and
Table 2-7 on page 2-6
Networks
3 Global
0.70%
1.20%
2.75%
15.65
15.65
Max.
Used
250
250
100
300
51.5
6.0
2.5
1.5
32
1
Units
MHz
MHz
ms
ps
ns
µs
ns
ns
%
ns
ns
ns
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