AGLE3000V2-FFG896 ACTEL [Actel Corporation], AGLE3000V2-FFG896 Datasheet - Page 107

• Manufacturer Part Number: AGLE3000V2-FFG896
• Description: IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
• Manufacturer: ACTEL [Actel Corporation]

Table 2-136 • IGLOOe CCC/PLL Specification
Note:
Figure 2-40 • Peak-to-Peak Jitter Definition
Parameter
Clock Conditioning Circuitry Input Frequency f
Clock Conditioning Circuitry Output Frequency f
Serial Clock (SCLK) for Dynamic PLL
Delay Increments in Programmable Delay Blocks
Number of Programmable Values in Each Programmable Delay
Block
Input Cycle-to-Cycle Jitter (peak magnitude)
CCC Output Peak-to-Peak Period Jitter F
Acquisition Time
Tracking Jitter
Output Duty Cycle
Delay Range in Block: Programmable Delay 1
Delay Range in Block: Programmable Delay 2
Delay Range in Block: Fixed Delay
Notes:
1. This delay is a function of voltage and temperature. See
2. T
3. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input
for deratings.
clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period
jitter parameter.
J
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 160 MHz
= 25°C, V
Peak-to-peak jitter measurements are defined by T
Output Signal
For IGLOOe V2 Devices, 1.2 V DC Core Supply Voltage
CC
= 1.5 V
1, 2
4
CCC_OUT
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
1, 2
1, 2
IN_CCC
1, 2
OUT_CCC
A dv a n c e v 0. 3
T
period_max
peak-to-peak
Table 2-6 on page 2-6
Network
1 Global
0.50%
1.00%
2.50%
= T
0.025
Used
Min.
0.75
48.5
T
2.3
1.5
period_min
period_max
Max Peak-to-Peak Period Jitter
IGLOOe DC and Switching Characteristics
External
FB Used
0.75%
1.50%
3.75%
Typ.
– T
580
5.7
period_min
and
Table 2-7 on page 2-6
Networks
3 Global
0.70%
1.20%
2.75%
20.86
20.86
Max.
Used
0.25
.
160
160
300
51.5
6.0
60
32
4
3
Units
MHz
MHz
ms
ps
ps
ns
µs
ns
ns
ns
ns
ns
%
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