LC4032B-10T44I LATTICE [Lattice Semiconductor], LC4032B-10T44I Datasheet - Page 2

• Manufacturer Part Number: LC4032B-10T44I
• Description: 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Table 2. ispMACH 4000Z Family Selection Guide
ispMACH 4000 Introduction
The high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend
of Lattice’s two most popular architectures: the ispLSI
the ispMACH 4000 architecture focuses on significant innovations to combine the highest performance with low
power in a flexible CPLD family.
The ispMACH 4000 combines high speed and low power with the flexibility needed for ease of design. With its
robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil-
ity, routing, pin-out retention and density migration.
The ispMACH 4000 family offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O com-
binations in Thin Quad Flat Pack (TQFP) and Fine Pitch BGA (fpBGA) packages ranging from 44 to 256 pins/balls.
Table 1 shows the macrocell, package and I/O options, along with other key parameters.
The ispMACH 4000 family has enhanced system integration capabilities. It supports 3.3V (4000V), 2.5V (4000B)
and 1.8V (4000C/Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely
driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The ispMACH
4000 also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up
resistors, pull-down resistors, open drain outputs and hot socketing. The ispMACH 4000 family members are 3.3V/
2.5V/1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary
scan testing capability also allows product testing on automated test equipment.
Overview
The ispMACH 4000 devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected
by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which
contain multiple I/O cells. This architecture is shown in Figure 1.
Macrocells
User I/O Options
t
t
t
f
Supply Voltage (V)
Standby Icc (µA)
Pins/Package
1. Preliminary information.
2. Advance information.
PD
S
CO
MAX
(ns)
(ns)
(ns)
(MHz)
ispMACH 4032ZC
56 csBGA
48 TQFP
267
3.5
2.2
3.0
1.8
32
32
20
1
ispMACH 4064ZC
132 csBGA
100 TQFP
56 csBGA
48 TQFP
®
32/64
2000 and ispMACH 4A. Retaining the best of both families,
250
4.0
2.8
3.3
1.8
64
25
2
ispMACH 4000V/B/C/Z Family Data Sheet
2
ispMACH 4128ZC
132csBGA
100 TQFP
64/96
128
220
4.5
2.9
3.9
1.8
30
2
ispMACH 4256ZC
132 csBGA
100 TQFP
176 TQFP
64/96/128
256
200
5.0
3.0
3.9
1.8
40
2