LC4032B-10T44I LATTICE [Lattice Semiconductor], LC4032B-10T44I Datasheet - Page 38

• Manufacturer Part Number: LC4032B-10T44I
• Description: 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Signal Descriptions
TMS
TCK
TDI
TDO
GOE0/IO, GOE1/IO
GND
NC
V
CLK0/I, CLK1/I, CLK2/I, CLK3/I
V
yzz
1. In some packages, certain I/O are only available for use as inputs. See the signal connections table for details.
CC
CCO0
, V
CCO1
Signal Names
Input – This pin is the IEEE 1149.1 Test Mode Select input, which is used to control
the state machine
Input – This pin is the IEEE 1149.1 Test Clock input pin, used to clock through the
state machine
Input – This pin is the IEEE 1149.1 Test Data In pin, used to load data
Output – This pin is the IEEE 1149.1 Test Data Out pin used to shift data out
These pins are configured to be either Global Output Enable Input or as general I/O
pins
Ground
Not Connected
The power supply pins for logic core
These pins are configured to be either CLK input or as an input
The power supply pins for each I/O bank
Input/Output
reference (alpha) and z is macrocell reference (numeric). z: 0-15
1
ispMACH 4032
ispMACH 4064
ispMACH 4128
ispMACH 4256
ispMACH 4384
ispMACH 4512
– These are the general purpose I/O used by the logic array. y is GLB
38
ispMACH 4000V/B/C/Z Family Data Sheet
Description
y: A-P, AX-HX
y: A-P, AX-PX
y: A-B
y: A-D
y: A-H
y: A-P