M52S16161A-10BG ESMT [Elite Semiconductor Memory Technology Inc.], M52S16161A-10BG Datasheet - Page 5

• Manufacturer Part Number: M52S16161A-10BG
• Description: 512K x 16Bit x 2Banks Synchronous DRAM
• Manufacturer: ESMT [Elite Semiconductor Memory Technology Inc.]

ESMT
AC OPERATING TEST CONDITIONS (V
Output
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
Elite Semiconductor Memory Technology Inc.
RAS to CAS delay
Row active time
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Row active to row active delay
Row precharge time
Row cycle time
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Number of valid output data
500
2.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
(Fig.1) DC Output Load circuit
then rounding off to the next higher integer.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
Minimum delay is required to complete write.
Parameter
Parameter
500
VDDQ
30 pF
VOH(DC) = VDDQ-0.2V, IOH = -0.1mA
VOL(DC) = 0.2V, IOL = 0.1mA
DD
CAS latency=3
CAS latency=2
CAS latency=1
=2.5V
Symbol
t
t
t
t
t
t
t
t
t
t
RRD
RCD
RP
RAS
RAS
RC
CDL
RDL
BDL
CCD
(min)
(min)
±
(min)
(min)
(min)
(min)
(max)
(min)
(min)
(min)
0.2V,T
A
= 0 C
°
Output
~ 70 C
0.9 x V
16
24
20
40
56
-8
tr / tf = 1 / 1
0.5 x V
0.5 x V
See Fig.2
° )
Value
DDQ
Version
(Fig.2) AC Output Load Circuit
DDQ
DDQ
/ 0.2
100
1
2
1
1
2
1
0
Z0=50
-10
20
30
20
50
70
Revision : 1.5
Publication Date : May. 2007
M52S16161A
Vtt =0.5x VDDQ
20 pF
50
Unit
CLK
CLK
CLK
CLK
ns
ns
ns
ns
us
ns
ea
Unit
ns
V
V
V
5/29
Note
1
1
1
1
1
2
2
2
3
4