AM29240EH AMD [Advanced Micro Devices], AM29240EH Datasheet

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... Two serial ports (UARTs) 20- and 25-MHz operating frequencies DRAM parity Am29245EH Microcontroller The low-cost Am29245 EH microcontroller is similar to the Am29240EH microcontroller, without the data cache and 32-bit multiplier. It includes the following features: 16-entry on-chip MMU with one TLB family Two-channel DMA controller ...

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... Am29240EH MICROCONTROLLER BLOCK DIAGRAM Parallel Port Control/Status Lines 4 6 Parallel Port Controller Serial Data Serial Ports Printer/Scanner Video Serializer/ Deserializer ROM Chip Selects Controller 4 Controller ROM Space PIA Memory Chip Selects Am29245EH MICROCONTROLLER BLOCK DIAGRAM Parallel Port Control/Status Lines 4 4 Parallel Port ...

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... The Am29240EH, Am29245EH, and Am29243EH RISC Microcontrollers User’s Manual (order #17741) describes the technical features, programming inter- face, on-chip peripherals, register set, and instruction set for the Am29240EH microcontroller series. Programming the 29K RISC Family (order #19243) in- ftp to cludes comprehensive information about the 29K family for the software developer ...

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... For a complete description of the technical features, on- chip peripherals, programming interface, register set, and instruction set, please refer to the Am29240EH, Am29245EH, and Am29243EH RISC Microcontrollers User’s Manual (order #17741). Am29240EH Microcontroller ...

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... K = 208-Lead Plastic Quad Flat Pack (PQR 208) SPEED OPTION – MHz – MHz – MHz DEVICE NUMBER/DESCRIPTION Am29240EH Enhanced RISC Microcontroller Am29245EH Enhanced RISC Microcontroller Am29243EH Enhanced RISC Data Microcontroller Valid planned to be supported in volume. Consult KC\W the local AMD sales office to confirm ...

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... Yes No Yes Yes Yes Yes 132 PQFP 168 PQFP 208 PQFP 12, 16, 20 MHz 16, 20 MHz Am29240 EH Microcontroller Series Am29240EH Am29243EH Controller Controller 4 Kbytes 4 Kbytes — 2 Kbytes 2 Kbytes 2-way 2-way 2-way 32 x 32-bit 32 x 32-bit 1 TLB 1 TLB 2 TLBs ...

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... DMA controller, a programmable I/O port, a parallel port two serial ports, and an interrupt controller. A video interface is also included in the Am29240EH and Am29245EH mi- crocontrollers for printer, scanner, and other imaging ap- plications. These facilities allow many simple systems to be built using only the Am29240EH microcontroller se- ries, external ROM, and/or DRAM memory ...

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... Bus compatibility ensures a convenient upgrade path for fu- ture systems. The Am29240EH microcontroller series is available in a 208-pin plastic quad flat-pack (PQFP) package. The Am29240EH microcontroller series is signal-compatible with the Am29200 and the Am29205 microcontrollers. ...

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... Data Formats The Am29240EH microcontroller series defines a word as 32 bits of data, a half-word as 16 bits, and a byte as 8 bits. The hardware provides direct support for word- integer (signed and unsigned), word-logical, word-Bool- ean, half-word integer (signed and unsigned), and char- acter data (signed and unsigned) ...

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... The page size for translation ranges from 1 Kbyte to 16 Mbytes in powers of 4. The Am29245EH and Am29240EH microcontrol- lers each have a single, 16-entry TLB. The Am29243EH microcontroller has dual 16-entry TLBs, each capable of mapping pages of different size ...

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... Current Processor Status Register. These signals have special hardening against metastable states, al- lowing them to be driven with slow-transition-time signals. LSYNC Line Synchronization (input, asynchronous) This signal indicates the start of a raster line. This signal is supported on the Am29240EH and Am29245EH mi- crocontrollers only. Am29240 EH Microcontroller Series 11 ...

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... MEMCLK is an output clock only. It operates at the sys- tem operating frequency, which is half of the INCLK fre- quency. Most processor inputs and outputs are synchronous to MEMCLK. Note that MEMCLK as an in- put is not supported on the Am29240EH microcontroller series. MEMDRV MEMCLK Drive Enable (input, internal pull-up resistor) The MEMDRV signal is reserved on the Am29240EH microcontroller series ...

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... This signal is used with video DRAMs to transfer data to the video shift register also used as an output en- able in normal video DRAM read cycles. This signal is supported on the Am29240EH and Am29245EH micro- controllers only. TRAP1–TRAP0 Trap Requests 1–0 (input, asynchronous, internal pull-ups) These inputs generate prioritized trap requests ...

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... This output is used to transmit serial data from Serial Port A. TXDB Transmit Data, Port B (output, asynchronous) This output is used to transmit data from Serial Port B. This signal is supported on the Am29240EH and Am29243EH microcontrollers only. UCLK UART Clock (input) This is an oscillator input for generating the UART (Seri- al Port) clock ...

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... Note: Pin 1 is marked for orientation Am29240EH Microcontroller Series Am29240 EH Microcontroller Series 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 ...

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... IDP2 100 IDP1 101 IDP0 102 51 GND 103 52 Reserved 104 Notes: 1. Defined as no-connect on Am29240EH microcontroller Pin Name Pin No. Pin Name Reserved 105 Reserved V 106 GND 107 GND Reserved 108 Reserved ...

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... GND 45 IDP0 1, 3 GND 51 IDP1 1, 3 GND 55 IDP2 1, 3 GND 69 IDP3 GND 80 INCLK Notes: 1. Defined as no-connect on Am29240EH microcontroller Pin No. Pin Name 91 INTR0 102 INTR1 107 INTR2 117 INTR3 2 127 LSYNC 137 MEMCLK 147 MEMDRV 154 ...

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... Am29240EH MICROCONTROLLER LOGIC SYMBOL INCLK MEMDRV TRIST 2 CNTL1–CNTL0 RESET WARN INTR3–INTR0 4 2 TRAP1–TRAP0 WAIT BOOTW 4 DREQD–DREQA GREQ PSTROBE PAUTOFD UCLK 2 RXDB–RXDA DTRA VCLK LSYNC TCK TDI TMS TRST MEMCLK VDAT ROMCS3–ROMCS0 ...

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Am29245EH MICROCONTROLLER LOGIC SYMBOL INCLK MEMDRV TRIST 2 CNTL1–CNTL0 RESET WARN INTR3–INTR0 4 2 TRAP1–TRAP0 WAIT BOOTW 2 DREQB–DREQA GREQ PSTROBE PAUTOFD UCLK RXDA DTRA VCLK LSYNC TCK TDI TMS TRST MEMCLK VDAT ...

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Am29243EH MICROCONTROLLER LOGIC SYMBOL INCLK MEMDRV TRIST 2 CNTL1–CNTL0 RESET WARN INTR3–INTR0 4 2 TRAP1–TRAP0 WAIT BOOTW 4 DREQD–DREQA GREQ PSTROBE PAUTOFD UCLK 2 RXDB–RXDA DTRA TCK TDI TMS TRST MEMCLK ...

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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . Voltage on any Pin with Respect to GND . . . . . . . . . –0 Stresses above ...

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SWITCHING CHARACTERISTICS over COMMERCIAL Operating Ranges No. Parameter Description 1 INCLK Period (=0.5T) 2 INCLK High Time 3 INCLK Low Time 4 INCLK Rise Time 5 INCLK Fall Time 6 MEMCLK Delay from INCLK 8 MEMCLK High Time 9 MEMCLK ...

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SWITCHING CHARACTERISTICS over COMMERCIAL Operating Ranges (continued) No. Parameter Description Asynchronous Input Pulse Width 17 LSYNC and PSYNC All others UCLK Period 18 VCLK Period 19 UCLK High Time VCLK High Time UCLK Low Time 20 VCLK Low Time UCLK ...

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SWITCHING WAVEFORMS 2.0 V INCLK 1 –0 MEMCLK 1.5 V 0.8 V 12a SYNCHRONOUS 1.5 V OUTPUTS SYNCHRONOUS INPUTS CASx Note: See Note 4 on page 23. ASYNCHRONOUS 1.5 ...

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SWITCHING WAVEFORMS (continued) MEMCLK A14–A1 Row Address R/W RAS3–RAS0 CAS3–CAS0 WE TR/OE ID31–ID0 IDP3–IDP0 Note: The RAS3–RAS0 signals are asserted and deasserted on the falling edge of MEMCLK . Figure 1. Simple 3/1 DRAM Read Cycle MEMCLK A14–A1 Row Address ...

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SWITCHING WAVEFORMS (continued) MEMCLK Row Address A14–A1 R/W RAS3–RAS0 CAS3–CAS0 WE TR/OE ID31–ID0 IDP3–IDP0 Note: The RAS3–RAS0 signals are asserted and deasserted on the falling edge of MEMCLK . MEMCLK Row Address A14–A1 R/W RAS3–RAS0 CAS3–CAS0 WE TR/OE ID31–ID0 IDP3–IDP0 ...

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SWITCHING WAVEFORMS (continued) MEMCLK Row Column Address A14–A1 Addr R/W RAS3–RAS0 CAS3–CAS0 WE TR/OE ID31–ID0 IDP3–IDP0 Figure 5. Simple 2/1 DRAM Read Cycle MEMCLK Row Column Address A14–A1 Addr R/W RAS3–RAS0 CAS3–CAS0 WE TR/OE ID31–ID0 Data IDP3–IDP0 Figure 6. Simple ...

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SWITCHING WAVEFORMS (continued) MEMCLK Row Column Address A14–A1 Addr R/W RAS3–RAS0 CAS3–CAS0 WE TR/ T/2 1.5 V ID31–ID0 IPD3–IDP0 Figure 7. 2/1 DRAM Page-Mode Read Cycle MEMCLK Row Column Address A14–A1 Addr R/W RAS3–RAS0 CAS3–CAS0 WE TR/OE Data ...

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SWITCHING WAVEFORMS (continued) MEMCLK DREQx DACKx Row Addr A14–A1 R/W RASx CASx WE TR/OE ID31–ID0 PIACSx PIAOE PIAWE Figure 9. Fly-By DMA Reads (Read Peripheral, Write DRAM)—3/1 DRAM Accesses ...

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SWITCHING WAVEFORMS (continued) MEMCLK DREQx DACKx Row Addr A14–A1 R/W RASx CASx WE TR/OE ID31–ID0 PIACSx PIAOE PIAWE Figure 10. Fly-By DMA Writes (Read DRAM, Write Peripheral)—3/1 DRAM Accesses ...

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SWITCHING WAVEFORMS (continued) MEMCLK DREQx DACKx Row A14–A1 Addr R/W RASx CASx WE TR/OE ID31–ID0 PIACSx PIAOE PIAWE Figure 11. Fly-By DMA Reads (Read Peripheral, Write DRAM)—2/1 DRAM Accesses ...

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SWITCHING WAVEFORMS (continued) MEMCLK DREQx DACKx Row A14–A1 Addr R/W RASx CASx WE TR/OE ID31–ID0 PIACSx PIAOE PIAWE Figure 12. Fly-By DMA Writes (Read DRAM, Write Peripheral)—2/1 DRAM Accesses ...

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... SWITCHING TEST CIRCUIT V VREF = 1.5 V Note: *All outputs except MEMCLK. MEMCLK is tested with I THERMAL CHARACTERISTICS The Am29240EH microcontroller series is specified for operation with case temperature ranges for a commercial temperature device. Case temperature is measured at the top center of the PQFP package as shown in Figure 13. JA ...

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PHYSICAL DIMENSIONS PQR 208, Trimmed and Formed Plastic Quad Flat Pack Pin 208 Pin 1 I.D. –A– Pin 52 See Detail X 3.20 3.60 0.25 Min. Notes: All measurements are in millimeters unless otherwise noted. Not to scale. For reference ...

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PQR 208 (continued) 0 Min. 0.30 0.05 R Gage 0.25 Plane 0.50 0.75 Notes: All measurements are in millimeters unless otherwise noted. Not to scale. For reference only 0.20 ...

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PHYSICAL DIMENSIONS (continued) Solder Land Recommendations—208-Lead PQFP 1.80 Typ. 0.50 Typ. 0.30 Typ. Notes: All measurements are in millimeters unless otherwise noted. Not to scale. For reference only. Trademarks Copyright 1997 Advanced Micro Devices, Inc. All rights reserved. AMD, the ...