AM29240EH AMD [Advanced Micro Devices], AM29240EH Datasheet - Page 13

• Manufacturer Part Number: AM29240EH
• Description: Enhanced High-Performance RISC Microcontrollers
• Manufacturer: AMD [Advanced Micro Devices]

RESET
Reset (input, asynchronous)
This input places the processor in the Reset mode. This
signal has special hardening against metastable states,
allowing it to be driven with a slow-rise-time signal.
ROMCS3–ROMCS0
ROM Chip Selects, Banks 3–0 (output, synchronous)
A Low level on one of these signals selects the memory
devices in the corresponding ROM bank. ROMCS3 se-
lects devices in ROM Bank 3, etc. The timing and access
parameters of each bank are individually programmable.
ROMOE
ROM Output Enable (output, synchronous)
This signal enables the selected ROM Bank to drive the
ID bus. It is used to prevent bus contention when switch-
ing between different ROM banks or switching between
a ROM bank and another device or DRAM bank.
RSWE
ROM Space Write Enable (output, synchronous)
This signal is used to write an alterable memory in a
ROM bank (such as an SRAM or Flash EPROM).
RXDA
Receive Data, Port A (input, asynchronous)
This input is used to receive serial data to Serial Port A.
RXDB
Receive Data, Port B (input, asynchronous)
This input is used to receive data to Serial Port B. This
signal
Am29243EH microcontrollers only.
STAT2–STAT0
CPU Status (output, synchronous)
These outputs indicate information about the processor
or the current access for the purposes of hardware
debug.
TCK
Test Clock Input
(input, asynchronous, pull-up resistor)
This input is used to operate the Test Access Port. The
state of the Test Access Port must be held if this clock is
held either High or Low. This clock is internally synchro-
nized to MEMCLK for certain operations of the Test Ac-
cess Port controller, so signals internally driven and
sampled by the Test Access Port are synchronous to
processor internal clocks.
is
supported
on
the
Am29240EH
Am29240 EH Microcontroller Series
P R E L I M I N A R Y
and
TDI
Test Data Input
(input, synchronous to TCK, pull-up resistor)
This input supplies data to the test logic from an external
source. It is sampled on the rising edge of TCK. If it is not
driven, it appears High internally.
TDMA
Terminate DMA (input/output, synchronous)
This signal is either an input or an output as controlled by
the corresponding DMA Control Register. As an input,
this signal can be asserted during an external DMA
transfer (non-fly-by) to terminate the transfer after the
current access. The TDMA input is ignored during fly-by
transfers. As an output, this signal is asserted to indicate
the final transfer of a sequence.
TDO
Test Data Output
(three-state output, synchronous to TCK)
This output supplies data from the test logic to an exter-
nal destination. It changes on the falling edge of TCK. It
is in the high-impedance state except when scanning is
in progress.
TMS
Test Mode Select
(input, synchronous to TCK, pull-up resistor)
This input is used to control the Test Access Port. If it is
not driven, it appears High internally.
TR/OE
Video DRAM Transfer/Output Enable
(output, synchronous)
This signal is used with video DRAMs to transfer data to
the video shift register. It is also used as an output en-
able in normal video DRAM read cycles. This signal is
supported on the Am29240EH and Am29245EH micro-
controllers only.
TRAP1–TRAP0
Trap Requests 1–0
(input, asynchronous, internal pull-ups)
These inputs generate prioritized trap requests. The
trap caused by TRAP0 has the highest priority. These
trap requests are disabled by the DA bit of the Current
Processor Status Register. These signals have special
hardening against metastable states, allowing them to
be driven with slow-transition-time signals.
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