AM29240EH AMD [Advanced Micro Devices], AM29240EH Datasheet - Page 23

• Manufacturer Part Number: AM29240EH
• Description: Enhanced High-Performance RISC Microcontrollers
• Manufacturer: AMD [Advanced Micro Devices]

Notes:
1. All outputs driving 80 pF, measured at V
2. VCLK and UCLK can be driven with TTL inputs. UCLK must be tied High if it is unused.
3. Maximum INCLK-to-MEMCLK delay can be decreased by 0.5 ns for each 10 mA increase in I
4. ID31–ID0 and IDP3–IDP0 are sampled on the rising edge of MEMCLK for all non-DRAM accesses, simple DRAM accesses,
5. LSYNC and PSYNC minimum width is two bit-times. A bit-time is one period of the internal video clock, which is determined by
6. Active VCLK edge depends on the CLKI bit in the Video Control Register.
7. LSYNC and PSYNC can be treated as synchronous signals by meeting the setup and hold times, though the synchronization
SWITCHING CHARACTERISTICS over COMMERCIAL Operating Ranges (continued)
No.
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For higher capacitance loads:
A. Add 1 ns output delay per 15 pF loading above 80 pF, up to 150 pF total. The minimum delay from PIAOE to PIACS x is 0 ns if
the capacitance loading on PIACS x is equal to or higher than the capacitance loading on PIAOE .
B. Add 1 ns output delay per 25 pF loading above 80 pF, up to 300 pF total. For 2/1 DRAM timing, in order to meet the setup time
(t
RAS3–RAS0 by more than 150 pF.
C. Add 1 ns of output delay for MEMCLK to drive an external load of 100 pF.
i.e., 6 ns maximum delay at I
and the first access of a DRAM page-mode access. ID31–ID0 and IDP3–IDP0 are sampled on the rising edge of CAS x for all
DRAM page-mode accesses, except the first access of a DRAM page-mode access. (See Figures 1–12 on pages 25–32.)
A. Applies to ID31–ID0 and IDP3–IDP0 for simple DRAM accesses and the first access of a DRAM page-mode access.
B. Applies to ID31–ID0 and IDP3–IDP0 for DRAM page-mode accesses, except the first access of a DRAM page-mode access.
the CLKDIV field in the Video Control Register and VCLK.
delay still applies.
ASR
When ID31–ID0 and IDP3–IDP0 are sampled on CAS x, there is no additional setup time required for ID31–ID0 and
IDP3–IDP0 when the parity is enabled.
) from A23–A0 to RAS3–RAS0 for DRAM, the capacitive loading of A23–A0 must not exceed the capacitance loading of
UCLK Period
VCLK Period
UCLK High Time
VCLK High Time
UCLK Low Time
VCLK Low Time
UCLK Rise time
VCLK Rise time
UCLK Fall Time
VCLK Fall Time
Synchronous Output Valid Delay
from VCLK Rise and Fall
Input Setup Time to VCLK Rise
and Fall
Input Hold Time to VCLK Rise
and Fall
RAS Low Time
CAS Low Time
Parameter Description
Asynchronous Input Pulse Width
LSYNC and PSYNC
All others
OL
= 20 mA.
Am29240 EH Microcontroller Series
OL
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 6
Notes 6, 7
Notes 6, 7
= 1.5 V and V
Test Conditions
P R E L I M I N A R Y
OH
= 1.5 V using the switching test circuit shown on page 33.
1
Note 5
Min
4T
30
25
10
10
10
50
13
8
8
0
0
0
0
1
0
16 MHz
Max
16
5
3
5
3
Note 5
Preliminary
Min
4T
25
20
50
13
8
6
8
6
0
0
0
0
1
9
0
20 MHz
OL
Max
14
5
3
5
3
up to the maximum of 20 mA,
Note 5
Min
4T
20
15
50
13
6
4
6
4
0
0
0
0
1
9
0
25 MHz
Max
14
5
3
5
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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