A29L320 AMICC [AMIC Technology], A29L320 Datasheet - Page 23

• Manufacturer Part Number: A29L320
• Description: 4M X 8 Bit / 2M X 16 Bit CMOS 3.3 Volt-only, Boot Sector Flash Memory
• Manufacturer: AMICC [AMIC Technology]

PRELIMINARY
RY/
The RY/
indicates whether an Embedded algorithm is in progress or
complete. The RY/
the final
is an open-drain output, several RY/
together in parallel with a pull-up resistor to VCC. (The
RY/
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is
ready to read array data (including during the Erase Suspend
mode), or is in the standby mode.
Table 10 shows the outputs for RY/
Timings”, “Timing Waveforms for Program Operation” and
“Timing Waveforms for Chip/Sector Erase Operation” for
more information.
I/O
Toggle Bit I on I/O
or Erase algorithm is in progress or complete, or whether the
device has entered the Erase Suspend mode. Toggle Bit I
may be read at any address, and is valid after the rising edge
of the final
program or erase operation), and during the sector erase
time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause I/O
(The system may use either
cycles.) When the operation is complete, I/O
After an erase command sequence is written, if all sectors
selected for erasing are
approximately 100µs, then returns to reading array data. If not
all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O
enters the Erase Suspend mode, I/O
However, the system must also use I/O
sectors are erasing or erase-suspended. Alternatively, the
system can use I/O
Polling").
If a program address falls within a protected sector, I/O
toggles for approximately 2µs after the program command
sequence is written, then returns to reading array data.
I/O
and stops toggling once the Embedded Program algorithm is
complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on I/O
algorithm, and to the Toggle Bit Timings figure in the "AC
Characteristics" section for the timing diagram. The I/O
I/O
graphical form. See also the subsection on " I/O
II".
6
6
6
BY : Read/ Busy
BY
: Toggle Bit I
figure shows the differences between I/O
also toggles during the erase-suspend-program mode,
pin is not available on the 44-pin SOP package)
WE
BY
WE
pulse in the command sequence. Since RY/
is a dedicated, open-drain output pin that
pulse in the command sequence (prior to the
6
BY
(September, 2005, Version 0.0)
indicates whether an Embedded Program
7
6
. Refer to Figure 6 for the toggle bit
(see the subsection on " I/O
status is valid after the rising edge of
6
and I/O
OE
protected, I/O
or
6
toggles. When the device
2
BY
CE
together to determine
BY
2
. Refer to “
to control the read
to determine which
6
pins can be tied
6
stops toggling.
stops toggling.
6
2
2
toggles
: Toggle Bit
and I/O
6
to toggle.
7
RESET
:
Data
2
BY
6
vs.
for
in
6
22
I/O
I/O
exceeded a specified internal pulse count limit. Under these
conditions I/O
indicates the program or erase cycle was not successfully
completed.
I/O
The "Toggle Bit II" on I/O
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the final
I/O
sectors that have been selected for erasure. (The system may
use either
cannot distinguish whether the sector is actively erasing or is
erase-suspended. I/O
device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information.
Refer to Table 10 to compare outputs for I/O
Figure 6 shows the toggle bit algorithm in flowchart form, and
the section " I/O
also the " I/O
Bit Timings figure for the toggle bit timing diagram. The I/O
vs. I/O
graphical form.
Reading Toggle Bits I/O
Refer to Figure 6 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O
toggle bit is toggling. Typically, a system would note and store
the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can
read array data on I/O
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O
on I/O
whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as I/O
is no longer toggling, the device has successfully completed
the program or erase operation. If it is still toggling, the device
did not complete the operation successfully, and the system
must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and I/O
system may continue to monitor the toggle bit and I/O
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Figure
6).
5
2
7
5
2
: Exceeded Timing Limits
: Toggle Bit II
toggles when the system reads at addresses within those
- I/O
indicates whether the program or erase time has
6
5
). If it is, the system should then determine again
figure shows the differences between I/O
0
OE
at least twice in a row to determine whether a
5
6
: Toggle Bit I" subsection. Refer to the Toggle
produces a "1." This is a failure condition that
or
2
: Toggle Bit II" explains the algorithm. See
CE
6
7
, by comparison, indicates whether the
WE
- I/O
to control the read cycles.) But I/O
AMIC Technology, Corp.
2
0
, when used with I/O
pulse in the command sequence.
6
, I/O
on the following read cycle.
5
2
A29L320 Series
went high. If the toggle bit
5
5
is high (see the section
has not gone high. The
2
and I/O
2
6
and I/O
, indicates
6
.
6
in
2
2
5