A29L320 AMICC [AMIC Technology], A29L320 Datasheet - Page 3

• Manufacturer Part Number: A29L320
• Description: 4M X 8 Bit / 2M X 16 Bit CMOS 3.3 Volt-only, Boot Sector Flash Memory
• Manufacturer: AMICC [AMIC Technology]

Pin Configurations
The host system can detect whether a program or erase
operation is complete by observing the RY /
reading the I/O
After a program or erase cycle has been completed, the
device is ready to read array data or accept another
command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
PRELIMINARY
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin. The Unlock Bypass mode
facilitates faster programming times by requiring only two
write cycles to program data instead of four.
-
an
7
(
Data
(September, 2005, Version 0.0)
internal
WP/ACC
RESET
RY/BY
Polling) and I/O
A20
A15
A14
A13
A12
A11
A10
WE
A18
A17
NC
NC
A9
A8
A7
A6
A5
A4
A3
A2
A1
algorithm
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
6
(toggle) status bits.
that
BY
automatically
pin, or by
A29L320V
2
TSOP (I)
contents of other sectors. The A29L320 is fully erased when
shipped from the factory.
The hardware sector protection feature disables operations
for both program and erase in any combination of the
sectors of memory. This can be achieved via programming
equipment.
The Erase Suspend/Erase Resume feature enables the user
to put erase on hold for any period of time to read data from,
or program data to, any other sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET pin terminates any operation in
progress and resets the internal state machine to reading
array data. The RESET pin may be tied to the system reset
circuitry. A system reset would thus also reset the device,
enabling the system microprocessor to read the boot-up
firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power
consumption is greatly reduced in both these modes.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
AMIC Technology, Corp.
BYTE
A16
VSS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OE
VSS
CE
A0
14
7
6
5
4
3
2
9
1
8
0
15
13
12
11
10
(A-1)
A29L320 Series