CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet - Page 82

• Manufacturer Part Number: CS8900-CQ3
• Description: Crystal LAN ISA Ethernet Controller
• Manufacturer: Cirrus Logic

memory via DMA). Table 19 describes the config-
uration bits in this register. Refer to Section 5.3 on
page 87 for a detailed description of Destination
Address filtering.
* Must also meet the criteria programmed into bits 8, C, D,
Bit
Bit Bit Name
82
C CRCerrorA When set, frames with bad CRC that
D
E LoRx Squelch When set, receiver squelch level
A IndividualA When set, frames with DA that
B
E ExtradataA When set, frames longer than 1518
6
8
9 AutoAUI/10BT When set, automatic interface
6
7
8
9
and E.
MulticastA When set, Multicast frames that pass
IAHashA When set, Individual Address frames
cuousA
RxOKA
Table 18. Physical Interface Configuration
Promis
Bit Name
Broad-
SerRxON
RuntA
castA
AUIonly
Table 19. Frame Acceptance Criteria
Register 13, LineCTL
Register 5, LRxCTL
that pass the hash filter are
accepted*.
When set, all frames are accepted*.
When set, frames with valid length
and CRC and that pass the DA filter
are accepted.
the hash filter are accepted*.
matches the IA at PacketPage base
+ 0158h are accepted*.
When set, all broadcast frames are
accepted*.
pass the DA filter are accepted.
When set, frames shorter than 64
bytes that pass the DA filter are
accepted.
bytes that pass the DA filter are
accepted (only the first 1518 bytes
are buffered).
When set, reception enabled.
When set, AUI selected (takes
precedence over AutoAUI/10BT).
selection enabled. When both bits
8 and 9 are clear, 10BASE-T
selected.
reduced by approximately 6 dB.
Operation
Operation
CIRRUS LOGIC PRODUCT DATA SHEET
5.2.2.3 Selecting which Events Cause Interrupts
The RxCFG register (Register 3) and the BufCFG
register (Register B) are used to determine which
receive events will cause interrupts to the host pro-
cessor. Table 21 describes the interrupt enable (iE)
bits in these registers.
* Must also pass the DA filter before there is an interrupt.
5.2.2.4 Choosing How to Transfer Frames
The RxCFG register (Register 3) and the BusCTL
register (Register 17) are used to determine how
frames will be transferred to host memory, as de-
scribed in Table 22.
Bit Bit Name
C CRCerroriE When set, there is an interrupt if a
D
8
E ExtradataiE When set, there is an interrupt if a
Bit
A
B
D
Table 21. Registers 3 and B Interrupt Configuration
7
F
RxOKiE
MissOvfloiE When set, there is an interrupt if
RuntiE
Crystal LAN™ ISA Ethernet Controller
Bit Name
RxDMAiE When set, there is an interrupt if
RxMissiE
RxDestiE
Rx128iE
Register B, BufCFG
Register 3, RxCFG
When set, there is an interrupt if a
frame is received with valid length
and CRC*.
frame is received with bad CRC*.
When set, there is an interrupt if a
frame is received that is shorter than
64 bytes*.
frame is received that is longer than
1518 bytes*.
one or more frames are trans-
ferred via DMA.
When set, there is an interrupt if a
frame is missed due to insufficient
receive buffer space.
When set, there is an interrupt
after the first 128 bytes of receive
data have been buffered.
the RxMISS counter overflows.
When set, there is an interrupt
after the DA of an incoming frame
has been buffered.
Table 20.
Operation
Operation
CS8900A
DS271PP3