CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet - Page 84

• Manufacturer Part Number: CS8900-CQ3
• Description: Crystal LAN ISA Ethernet Controller
• Manufacturer: Cirrus Logic

5.2.3.2 Early Interrupt Generation
The CS8900A support the following two early in-
terrupts that can be used to inform the host that a
frame is being received:
•
•
Like all Event bits, RxDest and Rx128 are set by
the CS8900A whenever the appropriate event oc-
curs. Unlike other Event bits, RxDest and Rx128
may be cleared by the CS8900A without host inter-
vention. All other event bits are cleared only by the
host reading the appropriate event register, either
directly or through the Interrupt Status Queue
(ISQ). (RxDest and Rx128 can also be cleared by
the host reading the BufEvent register, either di-
rectly or through the Interrupt Status Queue). Fig-
ure 22 provides a diagram of the Early Interrupt
process.
5.2.3.3 Acceptance Filtering
The third step of pre-processing is to determine
whether or not to accept the frame by comparing
the frame with the criteria programmed into the Rx-
84
RxDest: The RxDest bit (Register C, BufEvent,
Bit F) is set as soon as the Destination Address
(DA) of the incoming frame passes the DA fil-
ter. If the RxDestiE bit (Register B, BufCFG,
bit F) is set, the CS8900A generates a corre-
sponding interrupt. Once RxDest is set, the host
is allowed to read the incoming frame's DA (the
first 6 bytes of the frame).
Rx128: The Rx128 bit (Register C, BufEvent,
Bit B) is set as soon as the first 128 bytes of the
incoming frame have been received. If the
Rx128iE bit (Register B, BufCFG, bit B) is set,
the CS8900A generates a corresponding inter-
rupt. Once the Rx128 bit is set, the RxDest bit
is cleared and the host is allowed to read the
first 128 bytes of the incoming frame. The
Rx128 bit is cleared by the host reading the
BufEvent register (either directly or through the
Interrupt Status Queue) or by the CS8900A de-
tecting the incoming frame's End-of-Frame
(EOF) sequence.
CIRRUS LOGIC PRODUCT DATA SHEET
CTL register (Register 5). If the receive frame
passes the Acceptance filter, the frame is buffered,
either on chip or in host memory via DMA. If the
frame fails the Acceptance filter, it is discarded.
The results of the Acceptance filter are reported in
the RxEvent register (Register 4).
5.2.3.4 Normal Interrupt Generation
The final step of pre-processing is to generate any
enabled interrupts that are triggered by the incom-
ing frame. Interrupt generation occurs when the en-
tire frame has been buffered (up to the first 1518
bytes). For more information about interrupt gener-
ation, see Section 5.1 on page 79.
5.2.4 Held vs. DMAed Receive Frames
All accepted frames are either held in on-chip
RAM until processed by the host, or stored in host
memory via DMA. A receive frame that is held in
on-chip RAM is referred to as a held receive frame.
A frame that is stored in host memory via DMA is
a DMAed receive frame. This section describes
buffering and transferring held receive frames.
Section 5.4 on page 90 through Section 5.6 on
page 96 describe DMAed receive frames.
5.2.5 Buffering Held Receive Frames
If space is available, an incoming frame will be
temporarily stored in on-chip RAM, where it
awaits processing by the host. Although this re-
ceive frame now occupies on-chip memory, the
CS8900A does not commit the memory space to it
until one of the following two conditions is true:
1) The entire frame has been received and the host
Or:
2) The frame has been partially received, causing
has learned about the frame by reading the Rx-
Event register (Register 4), either directly or
through the ISQ.
either the RxDest bit (Register C, BufEvent, Bit
F) or the Rx128 bit (Register C, BufEvent, Bit
B) to become set, and the host has learned about
Crystal LAN™ ISA Ethernet Controller
CS8900A
DS271PP3