24LC21A-IP MicrochipTechnology, 24LC21A-IP Datasheet

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24LC21A-IP

Manufacturer Part Number
24LC21A-IP
Description
1K2.5VDualModeI2CSerialEEPROM
Manufacturer
MicrochipTechnology
Datasheet
FEATURES
• Single supply with operation down to 2.5V
• Completely implements DDC1 /DDC2
• Pin and function compatible with 24LC21
• Low power CMOS technology
• 2-wire serial interface bus, I
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to eight bytes
• 10,000,000 erase/write cycles guaranteed
• Data retention > 200 years
• ESD Protection > 4000V
• 8-pin PDIP and SOIC package
• Available for extended temperature ranges
DESCRIPTION
The Microchip Technology Inc. 24LC21A is a 128 x 8-
bit dual-mode Electrically Erasable PROM. This device
is designed for use in applications requiring storage
and serial transmission of configuration and control
information. Two modes of operation have been imple-
mented: Transmit-Only Mode and Bi-directional Mode.
Upon power-up, the device will be in the Transmit-Only
Mode, sending a serial bit stream of the memory array
from 00h to 7Fh, clocked by the VCLK pin. A valid high
to low transition on the SCL pin will cause the device to
enter the transition mode, and look for a valid control
byte on the I
the master, it will switch into Bi-directional Mode, with
byte selectable read/write capability of the memory
array using SCL. If no control byte is received, the
device will revert to the Transmit-Only Mode after it
receives 128 consecutive VCLK pulses while the SCL
pin is idle. The 24LC21A is available in a standard 8-pin
PDIP and SOIC package in both commercial and
industrial temperature ranges.
DDC is a trademark of the Video Electronics Standards Association.
I
2
C is a trademark of Philips Corporation.
1996 Microchip Technology Inc.
interface for monitor identification, including recov-
ery to DDC1
- 1 mA typical active current
- 10 A standby current typical at 5.5V
- Commercial (C):
- Industrial (I):
2
C bus. If it detects a valid control byte from
1K 2.5V Dual Mode I
-40 C to +85 C
0 C to +70 C
2
This document was created with FrameMaker 4 0 4
C
compatible
Preliminary
2
C Serial EEPROM
PACKAGE TYPES
BLOCK DIAGRAM
SDA
CONTROL
V
V
PDIP
SOIC
LOGIC
CC
SS
VCLK
I/O
SCL
V
NC
NC
NC
SS
V
NC
NC
NC
SS
CONTROL
24LC21A
MEMORY
LOGIC
1
2
3
4
1
2
3
4
XDEC
8
7
6
5
8
7
6
5
DS21160B-page 1
HV GENERATOR
PAGE LATCHES
R/W CONTROL
V
VCLK
SCL
SDA
SENSE AMP
CC
V
VCLK
SCL
SDA
EEPROM
ARRAY
CC
YDEC

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24LC21A-IP Summary of contents

Page 1

... SCL control byte is received, the device will revert to the Transmit-Only Mode after it receives 128 consecutive VCLK pulses while the SCL pin is idle. The 24LC21A is available in a standard 8-pin PDIP and SOIC package in both commercial and industrial temperature ranges. ...

Page 2

... ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* V ........................................................................7.0V CC All inputs and outputs w.r.t. V .... -0. Storage temperature ..........................- +150 C Ambient temp. with power applied .....- +125 C Soldering temperature of leads (10 seconds) .. +300 C ESD protection on all pins * Notice: Stresses above those listed under “Maximum ratings” may cause perma- nent damage to the device ...

Page 3

... Schmitt trigger inputs which provide noise and spike specification for standard operation. I Preliminary 24LC21A Units Remarks kHz (Note 1) ns (Note 1) ns After this period the first clock ...

Page 4

... FUNCTIONAL DESCRIPTION The 24LC21A is designed to comply to the DDC Stan- dard proposed by VESA (Figure 3-3) with the exception that it is not Access.bus capable. It operates in two modes, the Transmit-Only Mode and the Bi-directional Mode. There is a separate 2-wire protocol to support each mode, each having a separate clock input but sharing a common data line (SDA) ...

Page 5

... The bus must be con- trolled by a master device that generates the Bi-direc- tional Mode Clock (SCL), controls access to the bus and generates the START and STOP conditions, while the 24LC21A acts as the slave. Both master and slave can operate as transmitter or receiver, but the master 2 C bus, device determines which mode is activated ...

Page 6

... VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA. 2: The dash box and text “The 24LC21A and... inside dash box.” are added by Microchip Technology, Inc. 3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LC21A. ...

Page 7

... Note: Once switched into Bi-directional Mode, the 24LC21A will remain in that mode until power is removed. Removing power is the only way to reset the 24LC21A into the Transmit-only mode. 3.1.5 ACKNOWLEDGE Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte ...

Page 8

... After generating a START condition, the bus master transmits the slave address consisting of a 7-bit device code (1010000) for the 24LC21A. The eighth bit of slave address determines whether the master device wants to read or write to the 24LC21A (Figure 3-7). The 24LC21A monitors the bus for its corresponding slave address continuously ...

Page 9

... Page Write The write control byte, word address and the first data byte are transmitted to the 24LC21A in the same way byte write. But instead of generating a stop condition the master transmits up to eight data bytes to the 24LC21A which are temporarily stored in the on- chip page buffer and will be written into the memory after the master has transmitted a stop condition ...

Page 10

... Setting VCLK high allows normal write operations, while setting VCLK low prevents writing to any location in the array. Connecting the VCLK pin to V allow the 24LC21A to operate as a serial ROM, although this configuration would prevent using the device in the Transmit-Only Mode. ...

Page 11

... Then the master issues the control byte again but with the R/W bit set to a one. The 24LC21A will then issue an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LC21A discontinues transmission (Figure 7-2) ...

Page 12

... FIGURE 7-3: SEQUENTIAL READ BUS ACTIVITY MASTER DATA n CONTROL BYTE SDA LINE BUS ACTIVITY 8.0 PIN DESCRIPTIONS 8.1 SDA This pin is used to transfer addresses and data into and out of the device, when the device is in the Bi-direc- tional Mode. In the Transmit-Only Mode, which only allows data to be read from the device, data is also transferred on the SDA pin ...

Page 13

... NOTES: 1996 Microchip Technology Inc. Preliminary 24LC21A DS21160B-page 13 ...

Page 14

... NOTES: DS21160B-page 14 Preliminary 1996 Microchip Technology Inc. ...

Page 15

... Product Identification System To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed sales offices. 24LC21A — /P Package: Temperature Range: Device: 1996 Microchip Technology Inc Plastic DIP (300 mil Body), 8-lead ...

Page 16

W ORLDWIDE AMERICAS Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602 786-7200 Fax: 602 786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 ...

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