24LC21A-IP MicrochipTechnology, 24LC21A-IP Datasheet - Page 10

• Manufacturer Part Number: 24LC21A-IP
• Description: 1K2.5VDualModeI2CSerialEEPROM
• Manufacturer: MicrochipTechnology

24LC21A
FIGURE 4-3:
5.0
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a start condition followed by the control byte for
a write command (R/W = 0). If the device is still busy
with the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for the flow diagram.
FIGURE 5-1:
DS21160B-page 10
BUS ACTIVITY
MASTER
BUS ACTIVITY
SDA LINE
VCLK
ACKNOWLEDGE POLLING
Initiate Write Cycle
Send Control Byte
Write Command
Acknowledge
PAGE WRITE
ACKNOWLEDGE POLLING
FLOW
with R/W = 0
R
Condition to
S
T
A
T
S
(ACK = 0)?
Did Device
Send Start
Send Stop
Operation
Send
Next
CONTROL
Yes
BYTE
No
C
A
K
ADDRESS (1)
WORD
Preliminary
A
C
K
DATA (n)
6.0
When using the 24LC21A in the Bi-directional Mode,
the VCLK pin can be used as a write protect control pin.
Setting VCLK high allows normal write operations,
while setting VCLK low prevents writing to any location
in the array. Connecting the VCLK pin to V
allow the 24LC21A to operate as a serial ROM,
although this configuration would prevent using the
device in the Transmit-Only Mode.
WRITE PROTECTION
A
C
K
DATA n + 1
1996 Microchip Technology Inc.
A
C
K
DATA n + 7
SS
A
C
K
would
S
O
P
T
P