24LC21A-IP MicrochipTechnology, 24LC21A-IP Datasheet - Page 6

• Manufacturer Part Number: 24LC21A-IP
• Description: 1K2.5VDualModeI2CSerialEEPROM
• Manufacturer: MicrochipTechnology

24LC21A
FIGURE 3-3:
DS21160B-page 6
Note 1: The base flowchart is copyright
DDC Circuit Powered
2: The dash box and text “The 24LC21A and... inside dash box.” are added by Microchip Technology, Inc.
3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LC21A.
Display Power-on
from +5 volts
VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.
or
DISPLAY OPERATION PER DDC STANDARD PROPOSED BY VESA
No
No
No
No
Send EDID continuously
using Vsync as clock
Reset Vsync counter = 0
Switch to DDC2 mode.
Increment VCLK counter
Set Vsync counter = 0
Stop sending EDID.
Switch back to DDC1
Communication
transition on SCL
or start timer
transition state
Counter=128 or
(if appropriate)
DDC2 address
transition on
timer expired?
High to low
SCL, SDA or
VCLK lines?
Display has
Yes
Change on
High - low
Is Vsync
present?
optional
received?
is idle
SCL?
mode.
VCLK
cycle?
Valid
?
?
Yes
Yes
Yes
Yes
No
Yes
Yes
1993, 1994, 1995 Video Electronic Standard Association (VESA) from
No
No
No
Yes
Preliminary
Reset counter or timer
The 24LC21A was designed to
comply to the portion of flowchart inside dash box
specification to determine
idle. Display waiting for
DDC2 communication
See Access.bus
correct procedure.
Valid Access.bus
address byte.
Access.bus
transition on
High to low
received?
Is display
capable?
address
address?
DDC2B
SCL?
Yes
Yes
Yes
No
TM
No
No
Yes
No
1996 Microchip Technology Inc.
Respond to DDC2B
Receive DDC2B
command
command