24LC21A-IP MicrochipTechnology, 24LC21A-IP Datasheet - Page 8

• Manufacturer Part Number: 24LC21A-IP
• Description: 1K2.5VDualModeI2CSerialEEPROM
• Manufacturer: MicrochipTechnology

24LC21A
FIGURE 3-5:
FIGURE 3-6:
3.1.6
After generating a START condition, the bus master
transmits the slave address consisting of a 7-bit device
code (1010000) for the 24LC21A.
The eighth bit of slave address determines whether the
master device wants to read or write to the 24LC21A
(Figure 3-7).
The 24LC21A monitors the bus for its corresponding
slave
acknowledge bit if the slave address was true and it is
not in a programming mode.
DS21160B-page 8
Operation
SCL
SDA
SDA
IN
SDA
OUT
SCL
Read
Write
T
address
SU
SLAVE ADDRESS
:
T
STA
SU
:
STA
BUS TIMING START/STOP
BUS TIMING DATA
T
continuously.
SP
Slave Address
T
START
AA
1010000
1010000
T
F
T
HD
T
:
T
It
STA
LOW
HD
:
STA
generates
T
T
HIGH
HD
R/W
1
:
0
DAT
Preliminary
an
T
AA
FIGURE 3-7:
V
HYS
T
1
SU
START
:
DAT
0
T
T
SU
SU
:
SLAVE ADDRESS
STO
:
CONTROL BYTE
ALLOCATION
1
STO
0
T
1996 Microchip Technology Inc.
R
STOP
0
READ/WRITE
T
BUF
0
R/W
0
A