M24512 STMicroelectronics, M24512 Datasheet - Page 3

• Manufacturer Part Number: M24512
• Description: 512 Kbit Serial IC Bus EEPROM
• Manufacturer: STMicroelectronics

SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a slow-
er clock, the master must have an open drain out-
put, and a pull-up resistor must be connected from
the SCL line to V
value of the pull-up resistor can be calculated). In
most applications, though, this method of synchro-
nization is not employed, and so the pull-up resis-
tor is not necessary, provided that the master has
a push-pull (rather than open drain) output.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to trans-
fer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to V
pull-up resistor can be calculated).
Chip Enable (E2, E1, E0)
These chip enable inputs are used to set the value
that is to be looked for on the three least significant
bits (b3, b2, b1) of the 7-bit device select code.
These inputs may be driven dynamically or tied to
V
note that the V
CMOS compatible, not TTL compatible). When
unconnected, the E2, E1 and E0 inputs are inter-
nally read as V
Write Control (WC)
The hardware Write Control pin (WC) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC=V
Figure 3. Maximum R
CC
CC
or V
20
16
12
. (Figure 3 indicates how the value of the
8
4
0
10
SS
to establish the device select code (but
IL
IL
(see Table 7 and Table 8)
and V
CC
. (Figure 3 indicates how the
L
IH
Value versus Bus Capacitance (C
IL
levels for the inputs are
) or disable (WC=V
C BUS (pF)
100
fc = 400kHz
IH
fc = 100kHz
)
write instructions to the entire memory area. When
unconnected, the WC input is internally read as
V
When WC=1, Device Select and Address bytes
are acknowledged, Data bytes are not acknowl-
edged.
Please see the Application Note AN404 for a more
detailed description of the Write Control feature.
DEVICE OPERATION
The memory device supports the I
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note
AN1001 . Any device that sends data on to the bus
is defined to be a transmitter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is known as the master,
and the other as the slave. A data transfer can only
be initiated by the master, which will also provide
the serial clock for synchronization. The memory
device is always a slave device in all communica-
tion.
Start Condition
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device con-
tinuously monitors (except during a programming
cycle) the SDA and SCL lines for a START condi-
tion, and will not respond unless one is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state. A STOP condition terminates communica-
tion between the memory device and the bus mas-
ter. A STOP condition at the end of a Read
IL
, and write operations are allowed.
BUS
) for an I
1000
MASTER
V CC
2
C Bus
SDA
SCL
R L
C BUS
2
C protocol.
R L
AI01665
M24512
C BUS
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