M24512 STMicroelectronics, M24512 Datasheet - Page 6

• Manufacturer Part Number: M24512
• Description: 512 Kbit Serial IC Bus EEPROM
• Manufacturer: STMicroelectronics

M24512
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
NoAck. After each byte is transferred, the internal
byte address counter (the 7 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.
When the master generates a STOP condition im-
mediately after the Ack bit (in the “10
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not trig-
ger the internal write cycle.
During the internal write cycle, the SDA input is
disabled internally, and the device does not re-
spond to any requests.
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WC
BYTE WRITE
WC
PAGE WRITE
WC (cont'd)
PAGE WRITE
(cont'd)
NO ACK
DEV SEL
DEV SEL
DATA IN N
R/W
R/W
ACK
ACK
th
NO ACK
bit” time
BYTE ADDR
BYTE ADDR
ACK
ACK
BYTE ADDR
BYTE ADDR
ACK
ACK
DATA IN 1
DATA IN
NO ACK
NO ACK
DATA IN 2
AI01120B