MC9S12A256B ETC, MC9S12A256B Datasheet - Page 107

• Manufacturer Part Number: MC9S12A256B
• Description: device made up of standard HCS12 blocks and the HCS12 processor core
• Manufacturer: ETC

A.5 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.5.1 Startup
Table A-14 summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
A.5.1.1 POR
The release level V
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t
clock. The fastest startup time possible is given by n
A.5.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
A.5.1.3 External Reset
When external reset is asserted for a time greater than PW
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
Conditions are shown in Table A-4 unless otherwise noted
Num C
1
2
3
4
5
6
D Reset input pulse width, minimum input time
D Startup from Reset
D Interrupt pulse width, IRQ edge-sensitive mode
D Wait recovery startup time
T POR release level
T POR assert level
PORR
and the assert level V
CQOUT
Rating
Freescale Semiconductor, Inc.
For More Information On This Product,
Table A-14 Startup Characteristics
no valid oscillation is detected, the MCU will start using the internal self
Go to: www.freescale.com
PORA
are derived from the VDD supply. They are also valid
uposc
Symbol
PW
V
V
PW
n
t
.
PORR
PORA
WRS
RST
RSTL
RSTL
IRQ
MC9S12DP256B Device User Guide — V02.14
the CRG module generates an internal
Min
0.97
192
20
2
Typ
Max
2.07
196
14
Unit
n
t
t
ns
osc
cyc
V
V
osc
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