MC9S12A256B ETC, MC9S12A256B Datasheet - Page 115

• Manufacturer Part Number: MC9S12A256B
• Description: device made up of standard HCS12 blocks and the HCS12 processor core
• Manufacturer: ETC

A.7 SPI
A.7.1 Master Mode
Figure A-5 and Figure A-6 illustrate the master mode timing. Timing values are shown in Table A-18.
(CPOL 1)
(CPOL 0)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
1. If configured as output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
(INPUT)
MISO
MOSI
SCK
SCK
SS
1
2
5
9
MSB IN
MSB OUT
Figure A-5 SPI Master Timing (CPHA = 0)
2
6
Freescale Semiconductor, Inc.
4
2
For More Information On This Product,
1
4
BIT 6 . . . 1
Go to: www.freescale.com
BIT 6 . . . 1
9
MC9S12DP256B Device User Guide — V02.14
LSB IN
LSB OUT
12
11
10
3
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