MC9S12E Motorola, MC9S12E Datasheet - Page 122

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MC9S12E

Manufacturer Part Number
MC9S12E
Description
MC9S12E-Family Device User Guide V01.04
Manufacturer
Motorola
Datasheet

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Device User Guide — 9S12E128DGV1/D V01.04
B.4.1.4 External Reset
When external reset is asserted for a time greater than PW
the CRG module generates an internal
RSTL
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
B.4.1.5 Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.
B.4.1.6 Pseudo Stop and Wait Recovery
The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in
both modes. The controller can be woken up by internal or external interrupts. After t
the CPU starts
wrs
fetching the interrupt vector.
122
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