MC9S12E Motorola, MC9S12E Datasheet - Page 95

• Manufacturer Part Number: MC9S12E
• Description: MC9S12E-Family Device User Guide V01.04
• Manufacturer: Motorola

Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and
interrupts. System resets can be generated through external control of the RESET pin, through the clock
and reset generator module CRG or through the low voltage reset (LVR) generator of the voltage regulator
module. Refer to the CRG and VREG Block Guides for detailed information on reset generation.
5.2 Vectors
Table 5-1 lists interrupt sources and vectors in default order of priority.
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
$FFE8 to $FFEF
$FFE6, $FFE7
$FFE4, $FFE5
$FFE2, $FFE3
$FFE0, $FFE1
$FFDE, $FFDF
$FFDC, $FFDD
$FFDA, $FFDB
$FFD8, $FFD9
$FFD6, $FFD7
$FFD4, $FFD5
$FFD2, $FFD3
$FFD0, $FFD1
$FFCE, $FFCF
$FFC8 to $FFCD
$FFC6, $FFC7
$FFC4, $FFC5
Vector Address
External Reset, Power On Reset or Low
Voltage Reset (see CRG Flags Register
Unimplemented instruction trap
Pulse accumulator input edge
Standard Timer 0 channel 4
Standard Timer 0 channel 5
Standard Timer 0 channel 6
Standard Timer 0 channel 7
Pulse accumulator overflow
to determine reset source)
Standard Timer overflow
Clock Monitor fail reset
CRG Self Clock Mode
Freescale Semiconductor, Inc.
Interrupt Source
Real Time Interrupt
COP failure reset
Table 5-1 Interrupt Vector Locations
Port AD (KWU)
CRG PLL lock
For More Information On This Product,
XIRQ
SCI0
SCI1
SCI2
SWI
ATD
IRQ
SPI
Go to: www.freescale.com
Mask
CCR
None
None
None
None
None
X-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
Reserved
Reserved
Device User Guide — 9S12E128DGV1/D V01.04
COPCTL (CME, FCME)
SPICR1 (SPIE, SPTIE)
(TIE, TCIE, RIE, ILIE)
(TIE, TCIE, RIE, ILIE)
(TIE, TCIE, RIE, ILIE)
ATDCTL2 (ASCIE)
PTADIF (PTADIE)
PLLCR (LOCKIE)
PLLCR (SCMIE)
INTCR (IRQEN)
COP rate select
CRGINT (RTIE)
Local Enable
PACTL(PAOVI)
TSCR2 (TOI)
PACTL (PAI)
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
SCICR2
SCICR2
SCICR2
None
None
None
None
HPRIO Value
to Elevate
$DE
$DC
$DA
$D8
$D6
$D4
$D2
$D0
$CE
$C6
$C4
$F2
$F0
$E6
$E4
$E2
$E0
–
–
–
–
–
–
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