MC9S12E Motorola, MC9S12E Datasheet - Page 140

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MC9S12E

Manufacturer Part Number
MC9S12E
Description
MC9S12E-Family Device User Guide V01.04
Manufacturer
Motorola
Datasheet

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Device User Guide — 9S12E128DGV1/D V01.04
B.7.2 ATD Operating Characteristics - 3.3V Range
The Table B-11 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not
drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will
effectively be clipped.
B.7.3 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the
accuracy of the ATD.
B.7.3.1 Source Resistance:
Due to the input pin leakage current as specified in Table A-6 and Table A-7in conjunction with the
source resistance there will be a voltage drop from the signal source to the ATD input. The maximum
source resistance R
current. If device or operating conditions are less than worst case or leakage-induced error is acceptable,
larger values of source resistance are allowed.
Conditions are shown in Table A-4 unless otherwise noted; Supply Voltage 3.3V-10% <= V
Num C
NOTES:
1. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
2. Reduced accuracy see Table B-13 and Table B-14.
140
1
2
3
4
5
6
7
period of 16 ATD clocks.
D
C Differential Reference Voltage
D ATD Clock Frequency
D
D
D Recovery Time (V
P
Reference Potential
ATD 10-Bit Conversion Period
ATD 8-Bit Conversion Period
Reference Supply current
Conv, Time at 4.0MHz
Conv, Time at 2.0MHz ATD Clock f
Conv, Time at 2.0MHz ATD Clock f
S
specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage
DDA
Table B-11 3.3V ATD Operating Characteristics
=3.3 Volts)
Rating
Freescale Semiconductor, Inc.
For More Information On This Product,
2
ATD Clock f
Go to: www.freescale.com
Clock Cycles
Clock Cycles
ATDCLK
ATDCLK
ATDCLK
High
Low
(1)
1
V
N
T
T
Symbol
N
f
T
ATDCLK
CONV10
CONV10
RH
CONV10
CONV8
CONV8
t
I
V
V
REC
REF
RH
RL
-V
RL
V
V
DDA
Min
3.0
0.5
3.5
14
12
SSA
7
6
/2
DDA
<= 3.3V+10%
Typ
3.3
V
0.250
V
Max
DDA
3.6
2.0
28
14
26
13
20
DDA
7
/2
Cycles
Cycles
MHz
Unit
mA
µs
µs
µs
µs
V
V
V

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