MC9328MXL ETC, MC9328MXL Datasheet - Page 50

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MC9328MXL

Manufacturer Part Number
MC9328MXL
Description
i.MX Integrated Portable System Processor
Manufacturer
ETC
Datasheet

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Specifications
50
3.12 Multimedia Card/Secure Digital Host Controller
The DMA interface block controls all data routing between the external data bus (DMA access), internal
MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that
monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the
MMC/SD module (inner system) and the application (user programming).
Ref
No.
3a
3b
4a
4b
5a
5b
6a
6b
1
2
7
1.
2.
3.
C
C
C
CLK frequency at Data transfer Mode
(PP)
CLK frequency at Identification Mode
Clock high time
Clock low time
Clock fall time
Clock rise time
Input hold time
Input setup time
Output hold time
Output setup time
Output delay time
L
L
L
1
100 pF / 250 pF (10/30 cards)
25 pF (1 card)
250 pF (21 cards)
—10/30 cards
CMD_DAT Output
CMD_DAT Input
Bus Clock
1
1
1
3
Parameter
—10/30 cards
1
—10/30 cards
—10/30 cards
—10/30 cards
3
—10/30 cards
3
—10/30 cards
—10/30 cards
3
3
Figure 38. Chip-Select Read Cycle Timing Diagram
—10/30 cards
Table 18. SDHC Bus Timing Parameter Table
MC9328MXL Advance Information, Rev. 5
5a
Valid Data
2
4a
3a
Minimum
5.7/5.7
5.7/5.7
5.7/5.7
5.7/5.7
15/75
6/33
0
0
0
1.8V ± 0.10V
3b
6a
Valid Data
Maximum
(5.00)
(6.67)
10/50
14/67
25/5
400
16
7
1
3
3
2
Minimum
Valid Data
10/50
10/50
5/5
5/5
5/5
5/5
Valid Data
0
0
0
3.0 ± 0.30V
6b
5b
4b
Freescale Semiconductor
Maximum
10/50
10/50
25/5
400
14
MHz
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns

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