X40626V14I Xicor, X40626V14I Datasheet - Page 13

• Manufacturer Part Number: X40626V14I
• Description: Dual Voltage CPU Supervisor with 64K Serial EEPROM
• Manufacturer: Xicor

X40626
Figure 14. Sequential Read Sequence
X40626 Addressing
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
– a device type identifier that is ‘1010’ to access the
– one bit of ‘0’.
– next two bits are the device address. (S1 and S0)
– one bit of the slave command byte is a R/W bit. The
REV 1.1.15 2/11/04
array
R/W bit of the Slave Address Byte defines the opera-
tion to be performed. When the R/W bit is a one, then
a read operation is selected. A zero selects a write
operation. Refer to Figure 15.
Signals from
Signals from
the Slave
the Master
SDA Bus
S
Address
1
Slave
S
0
1
A
C
K
Data
(1)
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C
A
K
– After loading the entire Slave Address Byte from the
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is 00H on a power up condition.
The master must supply the two word address byte as
shown in Figure 15.
Data
(2)
SDA bus, the device compares the input slave byte
data to the proper slave byte. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
A
C
K
(n is any integer greater than 1)
Characteristics subject to change without notice.
Data
(n-1)
A
C
K
Data
(n)
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