X40626V14I Xicor, X40626V14I Datasheet - Page 17

• Manufacturer Part Number: X40626V14I
• Description: Dual Voltage CPU Supervisor with 64K Serial EEPROM
• Manufacturer: Xicor

X40626
TIMING DIAGRAMS
Bus Timing
WP Pin Timing
Write Cycle Timing
Nonvolatile Write Cycle Timing
Notes: (1) t
REV 1.1.15 2/11/04
SDA OUT
Symbol
SDA IN
t
WC
SCL
SCL
SDA
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
(1)
WC
SDA IN
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
SCL
t
WP
SU:STA
8th bit of Last Byte
t
HD:STA
t
F
Write Cycle Time
START
Parameter
t
SU:DAT
t
SU:WP
t
HIGH
ACK
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Clk 1
t
LOW
t
Slave Address Byte
HD:DAT
Condition
Stop
Min.
t
R
t
AA
Characteristics subject to change without notice.
t
WC
Typ.
t
t
HD:WP
DH
Clk 9
5
(1)
Condition
Start
Max.
10
t
BUF
t
SU:STO
Units
mS
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