X40626V14I Xicor, X40626V14I Datasheet - Page 3

• Manufacturer Part Number: X40626V14I
• Description: Dual Voltage CPU Supervisor with 64K Serial EEPROM
• Manufacturer: Xicor

X40626
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X40626 activates a Power
On Reset Circuit that pulls the RESET pin active. This
signal provides several benefits.
– It prevents the system microprocessor from starting
– It prevents the processor from operating prior to sta-
– It allows time for an FPGA to download its configura-
– It prevents communication to the EEPROM, greatly
When V
for t
RESET allowing the system to begin operation.
LOW VOLTAGE MONITORING
During operation, the X40626 monitors the V
and asserts RESET if supply voltage falls below a pre-
set minimum V
microprocessor from operating in a power fail or brown-
out condition. The RESET signal remains active until
the voltage drops below 1V. It also remains active until
V
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to LOW
periodically, while SCL is HIGH (this is a start bit) prior to
the expiration of the watchdog time-out period to prevent
a RESET signal. The state of two nonvolatile control bits
Figure 1. Set V
REV 1.1.15 2/11/04
CC
SCL
to operate with insufficient voltage.
bilization of the oscillator.
tion prior to initialization of the circuit.
reducing the likelihood of data corruption on power up.
SDA
WP
returns and exceeds V
PURST
CC
exceeds the device V
(200ms nominal) the circuit releases
0 1 2 3 4 5 6 7
TRIP
TRIP
. The RESET signal prevents the
A0H
Level Sequence (V
TRIP
for 200ms.
TRIP
0 1 2 3 4 5 6 7
threshold value
CC
V
P
/V
= 12-15V
00H
2MON
CC
www.xicor.com
level
= desired V
*for V
for V
TRIP
0 1 2 3 4 5 6 7
VTRIP2
in the Status Register determine the watchdog timer
period. The microprocessor can change these watchdog
bits, or they may be “locked” by tying the WP pin HIGH.
EEPROM INADVERTENT WRITE PROTECTION
When RESET goes active as a result of a low voltage
condition or Watchdog Timer Time-Out, any in-progress
communications are terminated. While RESET is
active, no new communications are allowed and no
non-volatile write operation can start. Non-volatile
writes in-progress when RESET goes active are
allowed to finish.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
V
The X40626 is shipped with a standard V
(V
operating and storage conditions. However, in applica-
tions where the standard V
higher precision is needed in the V
X40626 threshold may be adjusted. The procedure is
described below, and uses the application of a nonvola-
tile control signal.
Setting the V
This procedure is used to set the V
lower voltage value. It is necessary to reset the trip
point before setting the new value.
The V
sequence.
address is 01H
CC
TRIP
address is 0DH
/V
xxH*
TRIP
CC
2MON
) voltage. This value will not change over normal
and V2MON must be tied together during this
values, WP = 12-15V when WEL bit set)
THRESHOLD RESET PROCEDURE
TRIP
Characteristics subject to change without notice.
Voltage
0 1 2 3 4 5 6 7
TRIP
00H
is not exactly right, or if
TRIP
TRIP
to a higher or
CC
value, the
threshold
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