MT8LSDT3264A Micron Technology, MT8LSDT3264A Datasheet - Page 20

• Manufacturer Part Number: MT8LSDT3264A
• Description: SYNCHRONOUS DRAM MODULE
• Manufacturer: Micron Technology

Table 21: Serial Presence-Detect EEPROM AC Operating Conditions
V
NOTE:
32,64 Meg x 64 SDRAM DIMMs
SD8_16C32_64x64AG_C.fm - Rev. C 11/02
1. The SPD EEPROM WRITE cycle time (
PARAMETER/CONDITION
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can
start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
ClockHIGHperiod
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
DD
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
= +3.3V ±0.3V; All voltages referenced to V
SDA OUT
SDA IN
SCL
t SU:STA
t F
SPD EEPROM TIMING DIAGRAM
t
WRC) is the time from a valid stop condition of a write sequence to the end of
t HD:STA
t LOW
t AA
SS
t HIGH
t HD:DAT
20
SYMBOL
t
t
t
t
t
HD:DAT
HD:STA
SU:DAT
SU:STO
SU:STA
t
t
t
t
HIGH
t DH
LOW
f
WRC
t
t
BUF
SCL
AA
DH
t
t
t
F
R
I
t R
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t SU:DAT
MIN
300
250
0.3
4.7
4.7
4.7
4.7
168-PIN SDRAM DIMMs
0
4
4
256MB / 512MB (x64)
MAX
300
100
100
3.5
10
–
1
t SU:STO
t BUF
UNITS
KHz
UNDEFINED
ms
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
©2002, Micron Technology Inc.
NOTES
1