MT8LSDT3264A Micron Technology, MT8LSDT3264A Datasheet - Page 3

• Manufacturer Part Number: MT8LSDT3264A
• Description: SYNCHRONOUS DRAM MODULE
• Manufacturer: Micron Technology

Table 6:
Pin numbers may not correlate with symbols. Refer to the Pin Assignment table for pin number and symbol information.
32,64 Meg x 64 SDRAM DIMMs
SD8_16C32_64x64AG_C.fm - Rev. C 11/02
60, 65-67, 69-72, 74-77, 86-89,
2-5, 7-11, 13-17, 19-20, 55-58,
28, 29, 46, 47, 112, 113, 130,
33 - 38, 117 - 121, 123, 126
91-95, 97-101, 103-104,
139-142, 144, 149-151,
153-156,158-161
42, 79, 125, 163
PIN NUMBERS
30, 45,114, 129
27, 111, 115
165-167
63, 128
39, 122
131
83
82
Pin Descriptions
DQMB0-DQMB7
RAS#, CAS#,
CKE0, CKE1
DQ0-DQ63
SYMBOL
BA0, BA1
CK0-CK3
SA0-SA2
S0# -S3#
A0-A12
WE#
SDA
SCL
Output
Output
Input/
Input/
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
DESCRIPTION
Command Inputs: RAS#, CAS#, and WE# (along with S#)
define the command being entered.
Clock: CK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CK. CK also
increments the internal burst counter and controls the output
registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the
CK signal. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all device banks
idle) or CLOCK SUSPEND OPERATION (burst access in
progress). CKE is synchronous except after the device enters
power- down and self refresh modes, where CKE becomes
asynchronous until after exiting the same mode. The input
buffers, including CK, are disabled during power-down and
self refresh modes, providing low standby power.
Chip Select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.
Bank Address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto prcharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory arrary in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command.
Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Data I/O: Data bus.
Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-
detect portion of the module.
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
168-PIN SDRAM DIMMs
256MB / 512MB (x64)
©2002, Micron Technology Inc.