HYS64D128020GU-7-A Infineon, HYS64D128020GU-7-A Datasheet - Page 12

• Manufacturer Part Number: HYS64D128020GU-7-A
• Description: 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules
• Manufacturer: Infineon

Symbol
IDD4W
1. The module IDD values are calculated from the component IDD datasheet values as:
2. The module IDD values are calculated from the component IDD datasheet values as:
3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
4. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C
IDD2Q
IDD3N
IDD4R
IDD2P
IDD2F
IDD3P
IDD0
IDD1
IDD5
IDD6
IDD7
n * IDDx[component]
n * IDDx[component] + n * IDD3N[component]
n * IDDx[component]
2 * n * IDDx[component]
INFINEON Technologies
Operating, Standby and Refresh Currents (PC2100 and PC2700)
Active Standby Current : one bank active; active / precharge;CS >= VIH
Operating Current : one bank active; Burst = 2; writes; continuous burst;
Operating Current : one bank; active / precharge; tRC = tRC MIN; tCK =
Precharge Power-Down Standby Current : all banks idle; power-down
Operating Current : one bank active; Burst = 2; reads; continuous burst;
stable at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM.
address and control inputs changing once per clock cycle; 50% of data
address and control inputs changing once per clock cycle; 50% of data
DQS inputs changing twice per clock cycle; address and control inputs
Precharge Floating Standby Current : /CS >= VIH MIN, all banks idle;
Self-Refresh Current : CKE <= 0.2V; external clock on; tCK = tCK MIN
Active Power-Down Standby Current : one bank active; power-down
mode; CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and
MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and
Precharge Quiet Standby Current : /CS >= VIH MIN, all banks idle;
tCK MIN; DQ, DM, and DQS inputs changing once per clock cycle;
CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs
CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs
changing once per clock cycle, VIN = VREF for DQ, DQS and DM.
address and control inputs changing once every two clock cycles
Operating Current : four bank; four bank interleaving with BL=4;
Operating Current : one bank; active/read/precharge; Burst = 4;
outputs changing on every clock edge; CL = 2 for DDR200, and
outputs changing on every clock edge; CL = 2 for DDR200, and
Auto-Refresh Current : tRC = tRFC MIN, distributed refresh
DDR266A, CL=3 for DDR333; tCK = tCK MIN; IOUT = 0mA
Refer to the following page for detailed test conditions.
Refer to the following page for detailed test conditions.
DDR266A, CL=3 for DDR333; tCK = tCK MIN
mode; CKE <= VIL MAX; tCK = tCK MIN
for single bank modules (n: number of components per module bank)
for single bank modules (n: number of components per module bank)
changing once per clock cycle
for two bank modules (n: number of components per module bank)
Parameter/Condition
DM.
for two bank modules (n: number of components per module bank)
12
Unbuffered DDR-I SDRAM-Modules
HYS64/72D64000/128x20GU-7/8-A
512MB
1bank
MAX
1360
1440
1600
1560
2480
3040
112
400
224
144
560
x64
40
-7
512MB
1bank
MAX
1530
1620
1800
1755
2790
3420
126
450
252
162
630
x72
45
-7
2bank
MAX
2200
2320
1200
2560
2480
3280
3840
1GB
x64
288
960
640
368
80
-6
2bank
MAX
2475
2610
1080
1350
2880
2790
3690
4320
1GB
x72
324
720
414
90
-6
2002-09-10 (rev.0.81)
2bank
MAX
1920
2000
1120
2160
2120
3040
3600
1GB
x64
224
800
448
288
80
-7
2bank
MAX
2160
2250
1260
2430
2385
3420
4050
1GB
x72
252
900
504
324
90
-7
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
1, 3
1, 3
1, 3
1
2
4
2
2
2
2
1
1