HYS64D128320GU-5-B Infineon, HYS64D128320GU-5-B Datasheet - Page 28

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HYS64D128320GU-5-B

Manufacturer Part Number
HYS64D128320GU-5-B
Description
184-Pin Unbuffered Dual-In-Line Memory Modules
Manufacturer
Infineon
Datasheet
Table 17
Byte
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Data Sheet
Description
Number of SDRAM
Banks
Supported CAS
Latencies
CS Latencies
WE Latencies
SDRAM DIMM
Module Attributes
SDRAM Device
Attributes: General
Min. Clock Cycle Time
at CAS Latency = 2
Access Time from
Clock for
CL = 2
Minimum Clock Cycle
Time for CL = 1.5
Access Time from
Clock at
CL = 1.5
Minimum Row
Precharge Time
Minimum Row Act. to
Row Act. Delay
Minimum RAS to CAS
Delay
Minimum RAS Pulse
Width
Module Bank Density
(per Bank)
Addr. and Command
Setup Time
Addr. and Command
Hold Time
Operating, Standby and Refresh Currents (PC1600, –8) (cont’d)
t
t
RCD
RAS
t
RRD
4
CAS latency = 2 & 2.5 0C
CS latency = 0
Write latency = 1
unbuffered
10 ns
0.8 ns
not supported
not supported
20 ns
15 ns
20 ns
50 ns
256 MByte
1.1 ns
1.1 ns
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
30
128MB
1 rank
HEX
04
01
02
20
C0
A0
80
00
00
50
3C
50
32
20
B0
B0
64
Unbuffered DDR SDRAM Modules
256MB
1 rank
04
0C
01
02
20
C0
A0
80
00
00
50
3C
50
32
B0
B0
HEX
40
64
256MB
1 rank
HEX
04
0C
01
02
20
C0
A0
80
00
00
50
3C
50
32
40
B0
B0
72
512MB
2 ranks
HEX
04
0C
01
02
20
C0
A0
80
00
00
50
3C
50
32
40
B0
B0
64
SPD Contents
V1.1, 2003-07
512MB
2 ranks
04
0C
01
02
20
C0
A0
80
00
00
50
3C
50
32
40
B0
B0
HEX
72

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