GS832018 ETC, GS832018 Datasheet

GS832018

Manufacturer Part Number

GS832018

Description

(GS832018/32/36) Sync Burst SRAMs

Manufacturer

ETC

Datasheet

1.GS832018.pdf (25 pages)

Current page: 1 of 25
Download datasheet (670Kb)

100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline

• Single Cycle Deselect (SCD) operation

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• Pb-Free 100-lead TQFP package available

Functional Description

Applications

The GS832018/32/36T is a 37,748,736-bit high performance

synchronous SRAM with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications,

ranging from DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

Rev: 1.02 10/2004

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

operation

Through

Pipeline

3-1-1-1

2-1-1-1

Flow

2M x 18, 1M x 32, 1M x 36

36Mb Sync Burst SRAMs

Curr

tCycle

(x32/x36)

(x18)

Parameter Synopsis

1/25

-250 -225 -200 -166 -150 -133 Unit

285

350

205

235

2.5

4.0

6.5

265

320

195

225

2.7

4.4

7.0

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS832018/32/36T operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (V

from the internal circuits and are 3.3 V and 2.5 V compatible.

245

295

185

210

3.0

5.0

7.5

GS832018/32/36T-250/225/200/166/150/133

220

260

175

200

3.5

6.0

8.0

210

240

165

190

3.8

6.6

8.5

DDQ

185

215

155

175

4.0

7.5

8.5

) pins are used to decouple output noise

250 MHz–133 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Preliminary

Related parts for GS832018

GS832018 Summary of contents

Page 1

... ZZ signal stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS832018/32/36T operates 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (V from the internal circuits and are 3.3 V and 2.5 V compatible. ...

Page 2

Page 3

Page 4

... DQP Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 GS832036 100-Pin TQFP Pinout Top View 4/25 Preliminary DQP ...

Page 5

... DDQ Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 Description Address field LSBs and Address Counter preset Inputs Address Inputs Data Input and Output pins No Connect Byte Write—Writes all enabled bytes; active low ...

Page 6

... Power Down ZZ Control Note: Only x36 version shown for simplicity. Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 GS832018/32/36 Block Diagram Counter Load Register D Q Register ...

Page 7

... Note: The burst counter wraps to initial state on the 5th clock. Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 Pin Name State L LBO ...

Page 8

... All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “ ” and “ ” are only available on the x32 and x36 versions Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 ...

Page 9

... Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 State Diagram E E ...

Page 10

... The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low. Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 Simplified State Diagram X Deselect ...

Page 11

... Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 Simplified State Diagram with G X Deselect ...

Page 12

... Input Under/overshoot voltage must be –2 V > Vi < V Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 Description Voltage on V Pins DD ...

Page 13

... The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica- tions quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < V Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 Symbol Min. Typ. V 2.0 — ...

Page 14

... Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. DQ Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 Overshoot Measurement and Timing 50% V Symbol ...

Page 15

... FTInput Current Output Leakage Current (x36/x72) Output Leakage Current (x18) Output High Voltage Output High Voltage Output Low Voltage Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 Symbol Test Conditions ≥ ...

Page 16

Page 17

... asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 -250 -225 Min ...

Page 18

... tOE DQa–DQd Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 Pipeline Mode Timing Cont Deselect Write B Read C Single Write Single Write tKL tKL tKH tKH tKC tKC ...

Page 19

... E2 and E3 only sampled with ADSC tOE DQa–DQd Q(A) Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 Flow Through Mode Timing Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High ...

Page 20

... SRAM is recovering from Sleep mode. CK Setup Hold ADSP ADSC ZZ Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 Sleep Mode Timing Diagram tKH tKH tKC tKC tKL tKL tZZS ...

Page 21

... Lead Length — Y Coplanarity θ Lead Angle 0° Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 θ 0.10 0.15 1.40 1.45 0.30 0.40 0.20 — ...

Page 22

... GS832032T-150I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832018T-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...

Page 23

... GS832018GT-133I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832018T-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...

Page 24

... GS832036GT-133I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832018T-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...

Page 25

... Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 • Creation of new datasheet • Updated AC Characteristics table • Updated FT power numbers • Corrected Absolute Maximum Ratings table • Corrected Capacitance table Content • ...

Related keywords

GS832018 datasheet
GS832018 data sheet
GS832018 pdf datasheet
GS832018 component
GS832018 part
GS832018 distributor
GS832018 RoHS
GS832018 datasheet download