GS832018 ETC, GS832018 Datasheet - Page 5
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GS832018
Manufacturer Part Number
GS832018
Description
(GS832018/32/36) Sync Burst SRAMs
Manufacturer
ETC
Datasheet
1.GS832018.pdf
(25 pages)
TQFP Pin Description
Rev: 1.02 10/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ADSP, ADSC
Symbol
B
B
A
E
V
DQ
DQ
DQ
DQ
ADV
LBO
V
GW
V
BW
C
NC
A
CK
0
1
ZZ
FT
DDQ
E
G
A
, A
, B
, B
, E
DD
SS
2
B1
C
D
A
1
B
D
3
Type
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
5/25
Address Strobe (Processor, Cache Controller); active low
Address field LSBs and Address Counter preset Inputs
Byte Write Enable for DQ
Byte Write Enable for DQ
Burst address counter advance enable; active low
Global Write Enable—Writes all bytes; active low
Byte Write—Writes all enabled bytes; active low
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Sleep Mode control; active high
Clock Input Signal; active high
Data Input and Output pins
Output driver power supply
Output Enable; active low
Chip Enable; active high
Chip Enable; active low
GS832018/32/36T-250/225/200/166/150/133
I/O and Core Ground
Core power supply
Address Inputs
Description
No Connect
A
C
, DQ
, DQ
B
D
Data I/Os; active low
Data I/Os; active low
© 2003, GSI Technology
Preliminary