GS832018 ETC, GS832018 Datasheet - Page 7

• Manufacturer Part Number: GS832018
• Description: (GS832018/32/36) Sync Burst SRAMs
• Manufacturer: ETC

Mode Pin Functions
Note:
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in
the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.02 10/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2nd address
1st address
3rd address
4th address
Output Register Control
Power Down Control
Burst Order Control
Mode Name
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
10
11
00
10
00
01
11
11
00
01
10
Pin Name
7/25
LBO
ZZ
FT
Interleaved Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
2nd address
1st address
3rd address
4th address
H or NC
L or NC
State
GS832018/32/36T-250/225/200/166/150/133
H
H
L
L
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
00
11
10
Standby, I
Interleaved Burst
Flow Through
Linear Burst
Function
Pipeline
Active
10
00
01
11
DD
© 2003, GSI Technology
= I
SB
Preliminary
11
10
01
00
BPR 1999.05.18