CDP1805 Intersil Corporation, CDP1805 Datasheet - Page 8

• Manufacturer Part Number: CDP1805
• Description: CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer
• Manufacturer: Intersil Corporation

NOTES:
†
†
†
†
††
This Timing Diagram is used to show signal relationships only, and does not represent any specific machine cycle.
All measurements are referenced to 50% point of the wave forms.
Shaded areas indicate “don’t care” or undefined state. Multiple transitions may occur during this period.
For the run (RAM only) mode only.
For the run (RAM/ROM) mode only.
INTERNAL MEMORY
TO BUS (ME = LOW)
(I/O EXECUTION
DMA REQUEST
WRITE CYCLE)
READ CYCLE)
STATE CODES
CPU TO BUS
BUS TO CPU
(EXTERNAL
DATA FROM
DATA FROM
DATA FROM
INTERRUPT
ADDRESS
N0, N1, N2
(MEMORY
(MEMORY
(MEMORY
REQUEST
MEMORY
ENABLE)
MEMORY
EF1 - EF4
SELECT)
CYCLE)
CLOCK
†† EMS
CLEAR
MWR
WAIT
MRD
† ME
TPB
TPA
Q
t
t
PLH,
PLH
t
00
W
t
t
PLH,
PHL
0
t
PHL
t
t
01
PLH
SU
10
t
HIGH ORDER
ADDRESS BYTE
PLH
t
H
1
t
t
CDP1805AC, CDP1806AC
11
PLH,
PHL
t
SU
FIGURE 5. TIMING WAVEFORMS
t
t
WL
20
t
PHL
t
PHL
SU
2
21
t
H
30
DMA SAMPLED (S1, S2, S3)
3
t
t
8
PLH
PHL
t
31
t
PLH,
t
LOW ORDER
ADDRESS BYTE
SU
PLH,
INTERNAL RAM
IS ALLOWABLE
40
t
SAMPLED (S1, S2)
ACCESS TIME
PHL
t
PHL
4
41
INTERRUPT
DATA LATCHED
50
t
PHL
5
IN CPU
51
t
PHL
t
SU
60
t
SU
6
t
t
PLH
t
61
SU
SU
t
t
H
t
PLH,
PLH
SAMPLED END OF S0
t
PLH
t
70
H
t
t
H
H
t
PHL
t
7
SU
t
H
t
71
t
PHL
SU
FLAG LINES
t
H
t
00
PHL
t
H
0
01
t
t
PHL
t
PLH,
H
t
PLH