CDP1854 Intersil Corporation, CDP1854 Datasheet - Page 12

• Manufacturer Part Number: CDP1854
• Description: Programmable Universal Asynchronous Receiver/Transmitter (UART)
• Manufacturer: Intersil Corporation

NOTES:
NOTE:
1. If a start bit occurs at a time less than t
2. Read is the overlap of CS1, CS3, RD/WR = 1 and CS2 = 0. If a pending DA has not been cleared by a read of the Receiver Holding
3. OE and PE share terminal 15 and are also available as two separate bits in the status register.
1. Write is the overlap of TPB, CS1, CS3 = 1 and CS2, RD/WR = 0.
high-to-low transition of the clock. The start bit may be completely asynchronous with the clock.
Register by the time a new word is loaded into the Receiver Holding Register, the OE signal will come true.
RD/WR, CS2
CS3, CS1
(NOTE 1)
T BUS 0-
(NOTE 1)
(NOTE 1)
T BUS 7
R CLOCK
RSEL
(NOTE 2)
(NOTE 3)
(NOTE 3)
TPB
READ
TPB
SDI
DA
OE
PE
FE
(NOTE 1)
t
CH
t
DC
t
CC
t
CL
1
FIGURE 5. MODE 1 CPU INTERFACE (WRITE) TIMING DIAGRAM
2
t
TT
DC
FIGURE 4. MODE 1 RECEIVER TIMING DIAGRAM
t
3
TDA
before a high-to-low transition of the clock, the start bit may not be recognized until the next
START BIT
4
CDP1854A, CDP1854AC
CLOCK 7 1/2
SAMPLE
5
6
PARITY
7
5-53
t
RSW
16
t
DW
STOP BIT 1
1
2
HOLDING REGISTER
3
CLOCK 7 1/2 LOAD
4
t
TT
5
6
t
WRS
t
WD
7
8
9
t
t
COE
CDA
t
t
CPE
CFE