CDP1854 Intersil Corporation, CDP1854 Datasheet - Page 7

• Manufacturer Part Number: CDP1854
• Description: Programmable Universal Asynchronous Receiver/Transmitter (UART)
• Manufacturer: Intersil Corporation

CLEAR TO SEND (CTS):
When this input from peripheral is high, transfer of a
character to the Transmitter Shift Register and shifting of
serial data out is inhibited.
BIT
SIGNAL
ALSO AVAILABLE AT TERMINAL
† Polarity reversed at output terminal.
BIT SIGNAL: FUNCTION
0 DATA AVAILABLE (DA): When set high, this bit indicates that an entire character has been received and transferred to the Receiver
1 OVERRUN ERROR (OE): When set high, this bit indicates that the Data Available bit was not reset before the next character was
2 PARITY ERROR (PE): When set high, this bit indicates that the received parity bit does not compare to that programmed by the EVEN
3 FRAMlNG ERROR (FE): When set high, this bit indicates that the received character has no valid stop bit, i.e., the bit following the
4 EXTERNAL STATUS (ES): This bit is set high by a low-level input at Term. 38 (ES).
5 PERIPHERAL STATUS INTERRUPT (PSI): This bit is set high by a high-to-low voltage transition of Term. 37 (PSI). The INTERRUPT
6 TRANSMlTTER SHIFT REGISTER EMPTY (TSRE): When set high, this bit indicates that the Transmitter Shift Register has complet-
7 TRANSMlTTER HOLDING REGISTER EMPTY (THRE): When set high, this bit indicates that the Transmitter Holding Register has
Holding Register. This signal is also available at Term. 19 but with its polarity reversed.
transferred to the Receiver Holding Register. This signal OR’ed with PE is output at Term. 15.
PARITY ENABLE (EPE) control. This bit is updated each time a character is transferred to the Receiver Holding Register. This signal
OR’ed with OE is output at Term. 15.
parity bit (if programmed) is not a high-level voltage. This bit is updated each time a character is transferred to the Receiver Holding
Register. This signal is also available at Term. 14.
output (Term. 13) is also asserted (lNT = Iow) when this bit is set.
ed serial transmission of a full character including stop bit(s). It remains set until the start of transmission of the next character.
transferred its contents to the Transmitter Shift Register and may be reloaded with a new character. Setting this bit also sets the THRE
output (Term. 22) low and causes an INTERRUPT (lNT = low), if TR is high.
NOTES:
1. Interrupts will occur only after the IE bit in the Control Register (see Table 4) has been set.
2. THRE will cause an interrupt only after the TR bit in the Control Register (see Table 4) has been set.
DA (Receipt of Data)
THRE (Note 2)
(Ability to Reload)
THRE TSRE
(Transmitter Done)
PSI
(Negative Edge)
CTS
(Positive Edge when THRE TSRE)
SET (INT = LOW)
(NOTE 1)
CAUSE
TABLE 1. INTERRUPT SET AND RESET CONDITIONS
TABLE 2. STATUS REGISTER BIT ASSIGNMENT
THRE
22†
7
CDP1854A, CDP1854AC
Read of Data
Read of Status or Write of Character
Read of Status or Write of Character
Read of Status
Read of Status
TSRE
6
-
CONDITION
5-48
TRANSMITTER CLOCK (TCLOCK):
Clock input with a frequency 16 times the desired transmitter
shift rate.
PSI
5
-
RESET (INT = HIGH)
ES
4
-
TPB Leading Edge
TPB Leading Edge
TPB Leading Edge
TPB Trailing Edge
TPB Leading Edge
FE
14
3
TIME
PE
15
2
OE
15
1
19†
DA
0