CDP1854 Intersil Corporation, CDP1854 Datasheet - Page 15

• Manufacturer Part Number: CDP1854
• Description: Programmable Universal Asynchronous Receiver/Transmitter (UART)
• Manufacturer: Intersil Corporation

Functional Definitions for CDP1854A
Terminals Standard Mode 0
SIGNAL: FUNCTION
V
Positive supply voltage.
MODE SELECT (MODE):
A low-level voltage at this input selects Standard Mode 0
Operation.
V
Ground.
RECEIVER REGISTER DISCONNECT (RRD):
A high-level voltage applied to this input disconnects the
Receiver Holding Register from the Receiver Bus.
RECEIVER BUS (R BUS 7 - R BUS 0):
Receiver parallel data outputs.
PARITY ERROR (PE):
A high-level voltage at this output indicates that the received
parity does not compare to that programmed by the EVEN
PARITY ENABLE (EPE) control. This output is updated each
time a character is transferred to the Receiver Holding Reg-
ister. PE lines from a number of arrays can be bused
together since an output disconnect capability is provided by
the STATUS FLAG DISCONNECT (SFD) line.
FRAMING ERROR (FE):
A high-level voltage at this output indicates that the received
character has no valid stop bit, i.e., the bit following the parity
bit (if programmed) is not a high-level voltage. This output is
updated each time a character is transferred to the Receiver
Holding Register. FE lines from a number of arrays can be
bused together since an output disconnect capability is pro-
vided by the STATUS FLAG DISCONNECT (SFD) line.
OVERRUN ERROR (OE):
A high-level voltage at this output indicates that the DATA
AVAILABLE (DA) flag was not reset before the next charac-
ter was transferred to the Receiver Holding Register. OE
lines from a number of arrays can be bused together since
an output disconnect capability is provided by the STATUS
FLAG DISCONNECT (SFD) line.
STATUS FLAG DISCONNECT (SFD):
A high-level voltage applied to this input disables the three-
state output drivers for PE, FE, OE, DA, and THRE, allowing
these status outputs to be bus connected.
RECEIVER CLOCK (RCLOCK):
Clock input with a frequency 16 times the desired receiver
shift rate.
DATA AVAILABLE RESET (DAR):
A low-level voltage applied to this input resets the DA flip-
flop.
DD
SS
:
:
CDP1854A, CDP1854AC
5-56
DATA AVAILABLE (DA):
A high-level voltage at this output indicates that an entire
character has been received and transferred to the Receiver
Holding Register.
SERIAL DATA IN (SDl):
Serial data received at this input enters the receiver shift
register at a point determined by the character length. A
high-level voltage must be present when data is not being
received.
MASTER RESET (MR):
A high-level voltage at this input resets the Receiver Holding
Register, Control Register, and Status Register, and sets the
serial data output high.
TRANSMlTTER HOLDING REGISTER EMPTY (THRE):
A high-level voltage at this output indicates that the Transmit-
ter Holding Register has transferred its contents to the
Transmitter Shift Register and may be reloaded with a new
character.
TRANSMlTTER HOLDING REGISTER LOAD (THRL):
A low-level voltage applied to this input enters the character
on the bus into the Transmitter Holding Register. Data is
latched on the trailing edge of this signal.
TRANSMlTTER SHIFT REGISTER EMPTY (TSRE):
A high-level voltage at this output indicates that the Transmit-
ter Shift Register has completed serial transmission of a full
character including stop bit(s). It remains at this level until
the start of transmission of the next character.
SERIAL DATA OUTPUT (SDO):
The contents of the Transmitter Shift Register (start bit, data
bits, parity bit, and stop bit(s)) are serially shifted out on this
output. When no character is being transmitted, a high-level
is maintained. Start of transmission is defined as the
transition of the start bit from a high-level to a low-level
output voltage.
TRANSMlTTER BUS (T BUS 0 - T BUS 7):
Transmitter parallel data inputs.
CONTROL REGISTER LOAD (CRL):
A high-level voltage at this input loads the Control Register
with the control bits (PI, EPE, SBS, WLS1, WLS2). This line
may be strobed or hardwired to a high-level input voltage.
PARITY INHIBIT (PI):
A high-level voltage at this input inhibits the parity generation
and verification circuits and will clamp the PE output low. If
parity is inhibited the stop bit(s) will immediately follow the
last data bit on transmission.
STOP BIT SELECT (SBS):
This input selects the number of stop bits to be transmitted
after the parity bit. A high-level selects two stop bits, a low-
level selects one stop bit. Selection of two stop bits with five
data bits programmed selects 1.5 stop bits.