UPD64084 NEC, UPD64084 Datasheet - Page 33

• Manufacturer Part Number: UPD64084
• Description: THREE-DIMENSIONAL Y/C SEPARATION LSI WITH ON-CHIP MEMORY
• Manufacturer: NEC

14.2 System Configuration and Control Method
14.2.1
selection is made by a serial bus register of the PD64084. If the signal is input from a tuner when the ghost reducer is
used, a digital video signal input pin is selected by the
(such as those of a VCR, DVD, video camera, or game machine), the internal A/D converter of the PD64084 is made
valid, so that the video signal directly input to the PD64084 becomes valid.
14.2.2
ICs. When the ghost reducer is used (when signals are input from a tuner), the PD64031A generates burst lock clock
f
where system clocks (8f
supplied to the PD64031A by the PD64084 from the CLK8 pin.
the
(SA08h: D7 and D6) of the
changing the setting of this register depending on whether the ghost reducer is used or not, the analog switch can be
controlled by the signal output from the WP1 pin. In this way, the f
the C20O pin of the PD64031A is used.
SC
PD64084 be used.
PD64084, an analog switch is necessary in the input block of the f
PD64031A. When the ghost reducer is not used and the
, as shown in Figure 14-1. This f
When a video signal is input from a tuner or external pin, the input path of the video signal must be selected. This
For details on how to set the pins and registers, see Table 14-1 and Table 14-2 in Section 14.3.
When the PD64031A and PD64084 are digitally connected directly, the system clock must be shared by the two
When the ghost reducer is not used (when signals are input from an external source), the video signal is not input to
To switch the path of inputting f
This analog switch is controlled by the WP1 pin of the PD64031A. The WP1 pin is controlled by register DIR3DYC
A 20-MHz crystal oscillator that generates the basic clock for the f
For details on how to set the pins and registers, see Table 14-1 and Table 14-2 in Section 14.3.
PD64031A, and only the
Selecting video signal input path
Selecting mode according to clock and video signal input path
SC
and 4f
PD64031A (that selects a three-dimension Y/C separation digital connection mode). By
PD64084 operates. It is therefore necessary that the burst clock generated by the
SC
SC
) are generated. These system clocks are used by the
to the f
SC
goes through an external BPF and is input to the 8f
SC
BPF between the FSCO pin of the PD64031A and the FSCO pin of the
Data Sheet S16021EJ2V0DS
PD64084. When signals are input from other external pins
PD64084 operates alone, the 20-MHz clock output from
SC
SC
path can be changed.
BPF.
SC
generator should be provided to the
SC
PD64084, and are also
PLL of the
PD64084
PD64084,
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