CX28344 Conexant, CX28344 Datasheet - Page 141
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CX28344
Manufacturer Part Number
CX28344
Description
(CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
Manufacturer
Conexant
Datasheet
1.CX28344.pdf
(195 pages)
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CX28342/3/4/6/8 Data Sheet
3.5
Value after reset: 00(h)
Direction: Read only
OneSecltr
SrcChnl4
SrcChnl3
SrcChnl2
SrcChnl1
28348-DSH-001-B
Reserved
7
Reserved
One Second Interrupt—Set to indicate that the one second trigger occurred. Cleared when this
register is read.
Source Channel 4—Set to indicate that a source or one of the sources for interrupt on INTR*
pin is in channel 4. This bit is cleared when all the status bits in channel 4 indicating the
reasons for the interrupt are low.
Source Channel 3—Set to indicate that a source or one of the sources for interrupt on INTR*
pin is in channel 3. This bit is cleared when all the status bits in channel 3 indicating the
reasons for the interrupt are low.
Source Channel 2 —Set to indicate that a source or one of the sources for interrupt on INTR*
pin is in channel 2. This bit is cleared when all the status bits in channel 2 indicating the
reasons for the interrupt are low.
Source Channel 1—Set to indicate that a source or one of the sources for interrupt on INTR*
pin is in channel 1. This bit is cleared when all the status bits in channel 1 indicating the
reasons for the interrupt are low.
Status Registers
6
General Status Registers
General Status registers provide for general information about interrupt sources and
about the device. Status bits gather in common registers and are not spread, according
to the channels.
Source Channel Status Register (GSR00)
This is a general status register that indicates which channels or one-second trigger
are the sources for an asserted interrupt on INTR* pin. More than one bit can be high
at the same time because there can be multiple sources for interrupts. Only unmasked
interrupts are reflected in the SrcChnl1–SrcChnl4 bits, but the OneSecltr bit is the
status bit of the one-second trigger, even if its interrupt is masked.
Reserved
5
Mindspeed Technologies™
OneSecltr
4
SrcChnl4
3
SrcChnl3
2
SrcChnl2
1
SrcChnl1
0
Registers
3
-
29
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