AM29BDS128HD8VFI AMD [Advanced Micro Devices], AM29BDS128HD8VFI Datasheet - Page 3

• Manufacturer Part Number: AM29BDS128HD8VFI
• Description: 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

Am29BDS128H/Am29BDS640H
128 or 64 Megabit (8 M or 4 M x 16-Bit)
CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■ Single 1.8 volt read, program and erase (1.65 to 1.95 volt)
■ Manufactured on 0.13 µm process technology
■ VersatileIO™ (V
■ Simultaneous Read/Write operation
■ Programable Burst Interface
■ SecSi
■ Sector Architecture
■ Minimum 1 million erase cycle guarantee per sector
■ 20-year data retention at 125°C
■ 80-ball FBGA package (128 Mb) or 64-ball FBGA (64 Mb)
PERFORMANCE CHARCTERISTICS
■ Read access times at 75/66/54 MHz (C
■ Power dissipation (typical values, C
The Am29BDS640H has been retired and is not recommended for designs. For new designs, S29WS064K supersedes Am29BDS640H. Please refer to the S29WS-K family data sheet for
specifications and ordering information. The Am29BDS128H is available and is not affected by this revision.
— Device generates data output voltages and tolerates data
— 1.8V compatible I/O signals
— Data can be continuously read from one bank while
— Zero latency between read and write operations
— Four bank architecture:
— 2 Modes of Burst Read Operation
— Linear Burst: 8, 16, and 32 words with wrap-around
— Continuous Sequential Burst
— Up to 128 words accessible through a command sequence
— Up to 64 factory-locked words
— Up to 64 customer-lockable words
— Banks A and D each contain both 4 Kword sectors and 32
— Sixteen 4 Kword boot sectors
— Reliable operation for the life of the system
package
— Burst access times of 9.3/11/13.5 ns at industrial
— Synchronous latency of 49/56/69 ns
— Asynchronous random access times of 45/50/55 ns
— Burst Mode Read: 10 mA
— Simultaneous Operation: 25 mA
— Program/Erase: 15 mA
— Standby mode: 0.2 µA
input voltages as determined by the voltage on the V
executing erase/program functions in other bank
128 Mb has 16/48/48/16 Mbit banks
64 Mb has 8/24/24/8 Mbit banks
Kword sectors; Banks B and C contain ninety-six 32 Kword
sectors
Half of the boot sectors are at the top of the address range;
half are at the bottom of address range
temperature range
DATA SHEET
TM
(Secured Silicon) Sector region
IO
) Feature
L
= 30 pF)
L
=30 pF)
IO
pin
HARDWARE FEATURES
■ Handshaking feature
■ Hardware reset input (RESET#)
■ WP# input
■ Persistent Sector Protection
■ Password Sector Protection
■ ACC input: Acceleration function reduces programming
■ CMOS compatible inputs, CMOS compatible outputs
■ Low V
SOFTWARE FEATURES
■ Supports Common Flash Memory Interface (CFI)
■ Software command set compatible with JEDEC 42.4
■ Data# Polling and toggle bits
■ Erase Suspend/Resume
■ Unlock Bypass Program command
■ Burst Suspend/Resume
— Provides host system with minimum possible latency by
— Reduced Wait-state handshaking option further reduces
— Hardware method to reset the device for reading array data
— Write protect (WP#) function allows protection of the four
— A command sector protection method to lock combinations of
— Sectors can be locked and unlocked in-system at V
— A sophisticated sector protection method to lock
time; all sectors locked when ACC = V
standards
— Backwards compatible with Am29F and Am29LV families
— Provides a software method of detecting program and erase
— Suspends an erase operation to read data from, or program
— Reduces overall programming time when issuing multiple
— Suspends a burst operation to allow system use of the
monitoring RDY
initial access cycles required for burst accesses beginning on
even addresses
highest and four lowest 4 kWord boot sectors, regardless of
sector protect status
individual sectors and sector groups to prevent program or
erase operations within that sector
combinations of individual sectors and sector groups to
prevent program or erase operations within that sector using
a user-defined 64-bit password
operation completion
data to, a sector that is not being erased, then resumes the
erase operation
program command sequences
address and data bus, than resumes the burst at the previous
state
CC
write inhibit
Publication# 27024
Issue Date: May 10, 2006
IL
Rev: B Amendment: 3
CC
level