AM29DL400BB-120EC AMD [Advanced Micro Devices], AM29DL400BB-120EC Datasheet - Page 19

• Manufacturer Part Number: AM29DL400BB-120EC
• Description: 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles
4. Data bits DQ15–DQ8 are don’t cares for unlock and command
5. Address bits A17–A11 are don’t cares for unlock and
6. No unlock or command cycles required when bank is in read
7. The Reset command is required to return to reading array
Read (Note 6)
Reset (Note 7)
Program
Unlock Bypass
Unlock Bypass Program (Note 10) 2
Unlock Bypass Reset (Note 11)
Chip Erase
Sector Erase
Erase Suspend (Note 12)
Erase Resume (Note 13)
are write operations.
cycles in word mode.
command cycles, unless bank address (BA) is required.
mode.
data (or to the erase-suspend-read mode if previously in
Erase Suspend) when a bank is in the autoselect mode, or if
DQ5 is goes high (while the bank is providing status
information).
Manufacturer ID
Device ID,
Top Boot Block
Device ID,
Bottom Boot Block
Sector Protect
Verify (Note 9)
Command
Sequence
(Note 1)
Word
Word
Word
Word
Word
Word
Word
Word
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
1
1
1
4
4
4
4
4
3
2
6
6
1
Table 5. Am29DL400B Command Definitions
Addr Data Addr Data
XXX
AAA
AAA
AAA
AAA
AAA
AAA
XXX
AAA
AAA
555
555
555
555
555
555
555
555
RA
BA
BA
BA
First
RD
AA
AA
AA
AA
AA
AA
A0
AA
AA
B0
F0
90
30
P R E L I M I N A R Y
XXX
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
555
555
555
555
555
555
555
555
PA
Second
Am29DL400B
PD
55
55
55
55
55
55
00
55
55
(BA)AAA
(BA)AAA
(BA)AAA
(BA)AAA
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A17–A12 uniquely select any sector.
BA = Address of the bank that is being switched to autoselect
mode, is in bypass mode, or is being erased. Address bits A17–
A16 select a bank.
8. The fourth cycle of the autoselect command sequence is a
9. The data is 00h for an unprotected sector and 01h for a
10. The Unlock Bypass command is required prior to the Unlock
11. The Unlock Bypass Reset command is required to return to
12. The system may read and program in non-erasing sectors, or
13. The Erase Resume command is valid only during the Erase
(BA)555
(BA)555
(BA)555
(BA)555
Addr
AAA
AAA
AAA
AAA
555
555
555
555
read cycle. The system must provide the bank address to
obtain the manufacturer or device ID information.
protected sector. See the Autoselect Command Sequence
section for more information.
Bypass Program command.
reading array data when the bank is in the unlock bypass
mode.
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector
erase operation, and requires the bank address.
Suspend mode, and requires the bank address.
Bus Cycles (Notes 2–5)
Third
Data
A0
90
90
90
90
20
80
80
(BA)X00
(BA)X01
(BA)X02
(BA)X01
(BA)X02
Addr
(SA)
(SA)
AAA
AAA
X02
X04
555
555
PA
Fourth
220C
XX00
XX01
220F
Data
PD
AA
AA
0C
0F
01
00
01
Addr Data
2AA
2AA
555
555
Fifth
55
55
Addr
AAA
555
SA
Sixth
Data
10
30
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